lpc4310 NXP Semiconductors, lpc4310 Datasheet - Page 38

• Manufacturer Part Number: lpc4310
• Description: Lpc4350/30/20/10 32-bit Arm Cortex-m4/m0 Mcu; Up To 264 Kb Sram; Ethernet; Two High-speed Usbs; Advanced Configurable Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.12.5.1 Features
7.12.5 High-speed USB Host/Device/OTG interface (USB0)
7.12.6 High-speed USB Host/Device interface with ULPI (USB1)
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
Remark: Not available on all parts and packages. See
The USB OTG module allows the LPC4350/30/20/10 to connect directly to a USB Host
such as a PC (in device mode) or to a USB Device in host mode.
Remark: Not available on all parts and packages. See
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Read and write buffers to reduce latency and to improve performance.
8/16/32 data and 24 address lines wide static memory support.
16 bit and 32 bit wide chip select SDRAM memory support.
Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
Four chip selects for synchronous memory and four chip selects for static memory
devices.
Power-saving modes dynamically control EXTBUS_CKEOUT and EXTBUS_CLK
signals to SDRAMs.
Dynamic memory self-refresh mode controlled by software.
Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
Separate reset domains allow the for auto-refresh through a chip reset if desired.
Complies with Universal Serial Bus specification 2.0.
Complies with USB On-The-Go supplement.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals.
Supports all full-speed USB-compliant peripherals.
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
Contains UTMI+ compliant transceiver (PHY).
Supports interrupts.
This module has its own, integrated DMA engine.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 October 2010
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
Table
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© NXP B.V. 2010. All rights reserved.
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