peb20550 Infineon Technologies Corporation, peb20550 Datasheet - Page 78

• Manufacturer Part Number: peb20550
• Description: Extended Pcm Interface Controller
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
4.2.6.5 Interrupt Status Register (ISTA)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
The ISTA register should be read after an interrupt in order to determine the interrupt
source.
TIN
SFI
MFFI
MAC
PFI
PIM
bit 7
TIN
Timer
CMDR:ST,TIG = 1 has occurred. The TIN bit is reset by reading ISTA. It
should be noted that the interrupt generation is periodic, i.e. unless stopped
by writing to TIMR, the ISTA:TIN will be generated each time the timer
expires.
Signaling FIFO Interrupt; this interrupt is generated if there is at least one
valid entry in the CIFIFO indicating a change in a C/I or SIG channel.
Reading ISTA does not clear the SFI bit. Instead SFI is cleared if the CIFIFO
is empty which can be accomplished by reading all valid entries of the
CIFIFO or by resetting the CIFIFO by setting CMDR:CFR to 1.
MFFIFO Interrupt; the last MF-channel command (issued by CMDR:MFT1,
MFT0) has been executed and the EPIC is ready to accept the next
command. Additional information can be read from STAR:MFTO…MFFE.
MFFI is reset by reading ISTA.
Monitor channel Active interrupt; the EPIC has found an active monitor
channel. A new search can be started by reissuing the CMDR:MFSO
command. MAC is reset by reading ISTA.
PCM Framing Interrupt; the STAR:PSS bit has changed its polarity. To
determine whether the PCM-interface is synchronized or not, STAR must be
read. The PFI bit is reset by reading ISTA.
PCM Input Mismatch; this interrupt is generated immediately after the
comparison logic has detected a mismatch between a pair of PCM input
lines. The exact reason for the interrupt can be determined by reading the
PICM register. Reading ISTA clears the PIM-bit. A new PIM interrupt can
only be generated after the PICM register has been read.
SFI
H
interrupt;
MFFI
a
MAC
timer
78
interrupt
PFI
read
read
Detailed Register Description
previously
PIM
address: E
OMDR:RBS = 0
address: 1C
SIN
requested
PEB 2055
PEF 2055
H
bit 0
H
SOV
with