peb20550 Infineon Technologies Corporation, peb20550 Datasheet - Page 182

• Manufacturer Part Number: peb20550
• Description: Extended Pcm Interface Controller
• Manufacturer: Infineon Technologies Corporation

6-Bit Signaling Channel Scheme
This option is intended for IOM channels where the even time slot consists of an 8 bit
monitor channel and the odd time slot of a 6 bit signaling channel followed by the
2 monitor handshake bits MR and MX.
The monitor channel is handled by the MF handler according to the selected protocol,
handshake or non-handshake. If the handshake option is selected (IOM-2), the MF
handler controls the MR and MX bits according to the IOM-2 specification. If the
non-handshake option is selected (IOM-1), the MF handler sets both MR and MX bits to
logical 1; the MR and MX bit positions can then, if required, be accessed together with
the 6 bit SIG field via the even control memory address.
The 6 bit SIG channel can be accessed by the P for controlling codec filter devices. In
upstream direction each valid change in the SIG value is reported by interrupt to the P
and the CFI time slot address is stored in the CIFIFO (refer to chapter 5.5.2). The
change detection mechanism consists of a double last look logic with a programmable
period.
To initialize two consecutive CFI time slots for the 6 bit signaling channel scheme, the
CM codes as given in table 30 must be used:
Table 30
CM Address
Even time slot downstream
Odd time slot downstream
Even time slot upstream
Odd time slot upstream
Application hint:
Semiconductor Group
For some applications it is useful to switch the 6 SIG bits transparently
to and from the PCM interface. The monitor channel shall, however,
still be handled by the internal MF handler. For this purpose, a slightly
modified central D channel scheme can be used. This mode, which
has primarily been designed to switch the 16 kbit/s D channel to the
PCM interface, can be modified as follows: the odd control memory
address is written with the 64 kbit/s switching code “0001”, the CM
data field pointing to the desired PCM time slot. Since the MR and MX
bits are being switched, these must be carefully considered: in
upstream direction the two least significant bits of the PCM time slot
can be set to high impedance via the tristate field; in downstream
direction the two least significant bits of the PCM time slot must be
received at a logical 1 level since these bits will be logical ANDed at
the CFI with the downstream MR and MX bits generated by the MF
handler.
CM Code
1010
1011
1010
1010
182
CM Data
SIG 11
XXXXXXXX
actual value XX
stable value XX
B
Application Hints
B
B
B
PEB 2055
PEF 2055