peb20550 Infineon Technologies Corporation, peb20550 Datasheet - Page 51

• Manufacturer Part Number: peb20550
• Description: Extended Pcm Interface Controller
• Manufacturer: Infineon Technologies Corporation

4.2.1.4 PCM-Offset Upstream Register (POFU)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
OFU9..2
4.2.1.5 PCM-Clock Shift Register (PCSR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
OFD1..0
DRE
OFU1..0
URE
Semiconductor Group
bit 7
bit 7
OFU9
0
Offset Upstream bit 9…2.
These bits together with PCSR:OFU1..0 determine the offset of the PCM
frame in upstream direction. The following formulas apply for calculating the
required register value. BNU is the bit number in upstream direction marked
by the rising internal PFS-edge.
PCM mode 0:
PCM mode 1:
PCM mode 2:
Offset Downstream bits 1…0, see POFD register.
Downstream Rising Edge.
0…the PCM-data is sampled with the falling edge of PDC
1…the PCM-data is sampled with the rising edge of PDC
Offset Upstream bits 1…0, see POFU register.
Upstream Rising Edge.
0…the PCM-data is transmitted with the falling edge of PDC
1…the PCM-data is transmitted with the rising edge of PDC
OFU8
OFD1
H
H
OFU7
OFD0
OFU9..2 = mod
PCSR:OFU1..0 = 00
OFU9..1 = mod
PCSR:OFU0 = 0
OFU9..0 = mod
OFU6
DRE
51
OFU5
BPF
BPF
BPF
0
read/write
read/write
(BNU + 23)
(BNU + 47)
(BNU + 95)
read/write
read/write
Detailed Register Description
OFU4
OFU1
address: 4
address: 3
OMDR:RBS = 1
address: 26
OMDR:RBS = 1
address: 28
OFU3
OFU0
PEB 2055
PEF 2055
H
H
bit 0
bit 0
H
H
OFU2
URE