isp1704a NXP Semiconductors, isp1704a Datasheet - Page 26

• Manufacturer Part Number: isp1704a
• Description: Ulpi Hi-speed Usb Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1704A_1
Product data sheet
After the register configuration is complete:
By default, the clock is powered down when the ISP1704A enters UART mode. If the link
requires CLOCK to be running in UART mode, it can set the CLOCK_SUSPENDM bit in
the INTF_CTRL register (see
Transparent UART mode is exited by asserting the STP pin to HIGH or by toggling chip
select.
The INT pin is asserted and latched whenever an unmasked interrupt event occurs. When
the link detects INT as HIGH, it must wake-up the PHY from transparent UART mode by
asserting STP. When the PHY is in synchronous mode, the link can read the
USB_INTR_L register (see
that the ISP1704A does not implement optional Carkit Interrupt registers.
An alternative way to exit UART mode is to set chip select to deassert for more than
t
be put in default synchronous mode.
PWRDN
2. Set the DP_PULLDOWN and DM_PULLDOWN bits in the OTG_CTRL register (see
3. Set the TERMSELECT bit in the FUNC_CTRL register (see
4. Set the TXD_EN and RXD_EN bits in the CARKIT_CTRL register (see
5. Set the CARKIT_MODE bit in the INTF_CTRL register (see
1. A weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the
2. The 39
3. One clock cycle after DIR goes from LOW to HIGH, the ISP1704A will drive the data
4. UART buffers between DATA0 or DATA1 and DM or DP are enabled. Transparent
Section
(power-on default value).
Remark: Mandatory when a full-speed driver is used and optional for a low-speed
driver.
to logic 1. These two bits must be set together in one TXCMD.
Remark: The CARKIT_MODE, TXD_EN and RXD_EN bits must be set to logic 1.
The sequence of setting these register bits is ignored.
possible floating condition on these input pins when UART mode is enabled.
bus for five clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow
link. However, the link can start driving DATA0 to HIGH immediately after the
turnaround cycle.
UART mode is entered.
Remark: The DP pin will be slowly charged up to HIGH by the weak pull-up resistor.
The time needed depends on the capacitive loading on DP.
and then set it to assert. A power-on reset will be generated and the ULPI bus will
10.7) to logic 0.
serial termination resistors on the DP and DM pins will be enabled.
Rev. 01 — 28 July 2008
Section
Section
10.11) to determine the source of the interrupt. Note
10.6) to logic 1 before entering UART mode.
ULPI HS USB transceiver
Section
Section
ISP1704A
© NXP B.V. 2008. All rights reserved.
10.6) to logic 1.
10.5) to logic 0
Section
10.14)
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