isp1704a NXP Semiconductors, isp1704a Datasheet - Page 22

• Manufacturer Part Number: isp1704a
• Description: Ulpi Hi-speed Usb Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1704A_1
Product data sheet
9.2.1 Synchronous mode
9.2 ULPI modes
battery charger detection. The ISP1704A supports USB charger detection when used as
a peripheral transceiver. When used as a host or an OTG A-device transceiver, it is
recommended that the CHGR_DET_EN_N pin is deasserted.
When the CHGR_DET_EN_N pin is HIGH, it prevents automatic USB battery charger
detection from occurring. However, if the application manually sets DPVSRC_EN = 1, the
ISP1704A will still drive V
Once the charger detection procedure is completed and no charger is detected, the
ISP1704A will pause for 1 second and start detection again. This procedure is repeated
until a charger is detected.
While detecting the voltage on DM, the ISP1704A will perform an additional safety check
by ensuring that the DM voltage is below V
than V
detection. The ISP1704A will wait for V
charger detection. An example is when a user plugs the standard-A end of the USB cable
into a USB-to-PS2 adapter. This connects the B-device into the PS2 port of a PC, and
causes V
Leakage on DP and DM when a PS2 adapter is connected is 300 A (typical).
There is an internal RC circuit in the ISP1704A that oscillates at f
by the state machine governing the charger detection. Frequency f
to a 1 kHz clock. The 1 kHz clock is used to meet timing requirements of the USB battery
charger.
When disabling the DPVSRC_EN bit (manual charger detection is completed), the
ISP1704A requires a minimum delay of 200 s before the battery charger detection circuit
is fully disabled. Software must wait 200 s before enabling the DP pull up.
The ISP1704A ULPI interface can be programmed to operate in five modes. In each
mode, the signals on the data bus are reconfigured as described in the following
subsections. Setting more than one mode will lead to undefined behavior.
This is default mode. On power-up, and when CLOCK is stable, the ISP1704A will enter
synchronous mode.
In synchronous mode, the link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
This mode is used by the link to perform the following tasks:
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs) from the ISP1704A
th(se)
BUS
, then an illegal device is attached and the ISP1704A will not perform charger
to be shorted to DP and DM, making the PS2 port act like a charger.
Rev. 01 — 28 July 2008
DAT_SRC
on the DP line.
Section
BUS
th(se)
to fall and rise again before re-attempting
14.
(see
Table
59). If the DM voltage is greater
ULPI HS USB transceiver
clk(int)lp
clk(int)lp
ISP1704A
. This clock is used
© NXP B.V. 2008. All rights reserved.
is divided down
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