isp1562 NXP Semiconductors, isp1562 Datasheet - Page 86

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isp1562

Manufacturer Part Number
isp1562
Description
Hi-speed Universal Serial Bus Pci Host Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
20. References
21. Revision history
Table 128. Revision history
ISP1562_2
Product data sheet
Document ID
ISP1562_2
Modifications:
ISP1562_1
(9397 750 14223)
Release date
20070301
20050714
Table 127. Abbreviations
[1]
[2]
[3]
[4]
[5]
[6]
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Symbols and their descriptions have been updated, wherever applicable, to comply with the new
guidelines of NXP Semiconductors.
Table 2 “Pin
description for pins 18, 83, 85, 90 and 92.
Figure 4 “Power supply
also added a figure note.
Section 11 “USB Host Controller
to “Content of the base address register”.
Updated
Table 104 “ASYNCLISTADDR - Current Asynchronous List Address register bit allocation”
Table 105 “ASYNCLISTADDR - Current Asynchronous List Address register bit
changed LPL[19:0] to LPL[26:0].
Table 113 “Recommended operating
Table 114 “Static characteristics: I
min value for V
Table 115 “Static characteristics: digital
Table 124 “PCI clock and IO timing”
Acronym
STB
USB
VID
Universal Serial Bus Specification — Rev. 2.0
Open Host Controller Interface Specification for USB — Rev. 1.0a
Enhanced Host Controller Interface Specification for Universal Serial Bus —
Rev. 1.0
PCI Local Bus Specification — Rev. 2.2
PCI Bus Power Management Interface Specification — Rev. 1.1
The I
Section 12 “Current
2
description”: changed I/O details for pins 4 and 45 from I/O to O, and updated
C-bus Specification — Version 2.1
IL
.
Data sheet status
Product data sheet
Product data sheet
Description
Set-Top Box
Universal Serial Bus
Vendor ID
connection”: changed the value of capacitor on pin 18 from 20 F to 4.7 F;
Rev. 02 — 1 March 2007
…continued
consumption”.
registers”: changed the description in the table title for all registers
2
C-bus interface (SDA and
updated PCI reset timing section.
conditions”: added T
pins”: added max value for V
Change notice
-
-
j
.
SCL)”: added max value for V
HS USB PCI Host Controller
IH
and min value for V
Supersedes
ISP1562_1
-
© NXP B.V. 2007. All rights reserved.
description”:
ISP1562
IL
and
IH
.
86 of 93
and

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