isp1562 NXP Semiconductors, isp1562 Datasheet - Page 41

• Manufacturer Part Number: isp1562
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
Table 54.
Address: Content of the base address register + 14h
ISP1562_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30
29 to 7
6
5
4
3
2
1
0
The reserved bits should always be written with the reset value.
Symbol
MIE
OC
reserved -
RHSC
FNO
UE
RD
SF
WDH
SO
HcInterruptDisable - Host Controller Interrupt Disable register bit description
reserved
R/W
R/W
15
0
7
0
Description
Master Interrupt Enable:
0 — Ignore
1 — Disables interrupt generation because of events specified in other bits of this register.
This field is set after a hardware or software reset. Interrupts are disabled.
Ownership Change:
0 — Ignore
1 — disables interrupt generation because of ownership change.
Root Hub Status Change:
0 — Ignore
1 — Disables interrupt generation because of root hub status change.
Frame Number Overflow:
0 — Ignore
1 — Disables interrupt generation because of frame number overflow.
Unrecoverable Error:
0 — Ignore
1 — Disables interrupt generation because of unrecoverable error.
Resume Detect:
0 — Ignore
1 — Disables interrupt generation because of resume detect.
Start-of-Frame:
0 — Ignore
1 — Disables interrupt generation because of Start-of-Frame.
HcDoneHead Write-back:
0 — Ignore
1 — Disables interrupt generation because of HcDoneHead write-back.
Scheduling Overrun:
0 — Ignore
1 — Disables interrupt generation because of scheduling overrun.
[1]
RHSC
R/W
R/W
14
0
6
0
FNO
R/W
R/W
13
0
5
0
Rev. 02 — 1 March 2007
R/W
R/W
UE
12
0
4
0
reserved
[1]
R/W
R/W
RD
11
0
3
0
R/W
R/W
SF
10
0
2
0
HS USB PCI Host Controller
WDH
R/W
R/W
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1562
R/W
R/W
SO
8
0
0
0
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