ucb1400 NXP Semiconductors, ucb1400 Datasheet - Page 8

• Manufacturer Part Number: ucb1400
• Description: Audio Codec With Touch Screen Controller And Power Management Monitor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09611
Product data
Fig 6. AC Link audio output frame.
SDATA_OUT
END OF PREVIOUS
BIT_CLK
* See
AUDIO FRAME
SYNC
Table
FRAME
VALID
4.
8.3.2 AC-link audio output frame (SDATA_OUT)
slot(1)
(“1” = TIME SLOT CONTAINS VALID PCM DATA)
TAG PHASE
slot(2)
The audio output frame data streams correspond to the multiplexed bundles of all
digital output data targeting UCB1400’s DAC inputs, and control registers. Each audio
output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special
reserved time slot containing 16 bits which are used for AC-link protocol
infrastructure.
Slot 0: TAG:
flags the validity for the entire audio frame. If the ‘Valid Frame’ bit is a 1, this indicates
that the current audio frame contains at least one slot time of valid data. The next 12
bit positions sampled by UCB1400 indicate which of the corresponding 12 time slots
contain valid data. In this way, data streams of differing sample rates can be
transmitted across AC-link at its fixed 48 kHz audio frame rate.
Figure 6
slot 0 tag phase are used for primary/secondary codec addressing as described in
Section
81.4 ns
(12.288 MHz)
A new audio output frame begins with a LOW-to-HIGH transition of SYNC. SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, the UCB1400 samples the assertion of SYNC. This falling edge marks
the time when both sides of AC-link are aware of the start of a new audio frame. On
the next rising of BIT_CLK, the AC ’97 Controller transitions SDATA_OUT into the first
bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on
a rising edge of BIT_CLK, and subsequently sampled by UCB1400 on the following
falling edge of BIT_CLK. This sequence ensures that data transitions, and
subsequent sample points for both incoming and outgoing data streams are time
aligned.
TIME SLOT “VALID” BITS
slot(12)
8.4.
illustrates the time slot based AC-link protocol. (Note that Bits 1 and 0 of
“0”
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which
*
Rev. 02 — 21 June 2002
*
(48 kHz)
20.8 s
19
SLOT 1
0
19
Audio codec with touch screen controller
SLOT 2
DATA PHASE
0
and power management monitor
19
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
SLOT 3
0
UCB1400
19
SLOT 12
SN00221
0
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