ucb1400 NXP Semiconductors, ucb1400 Datasheet - Page 38

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ucb1400

Manufacturer Part Number
ucb1400
Description
Audio Codec With Touch Screen Controller And Power Management Monitor
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
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Product data
12.7 Power-down Control/Status register (index 0x26)
Table 23:
Register address: 0x26; default: 000X
Table 24:
This read/write register is used to program power-down states and monitor
subsystem readiness. The lower half of this register is read only status, a ‘1’
indicating that the subsection is ‘ready’. ‘Ready’ is defined as the subsection able to
perform in its nominal state. When this register is written, the bit values that come in
on AC-link will have no effect on read-only bits 0 - 7.
When the ‘Codec Ready’ indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that
the UCB1400 control and status registers are in a fully operational state. The AC ’97
Controller must further probe this Power-down Control/Status register to determine
exactly which subsections, if any, are ready.
Bit
D15 - D14
D13
D12
D11
D10
D9
D8
D7 - D4
D3
D2
D1
D0
Bit
Symbol
Bit
Symbol
Power-down Control/Status register
Description of Power-down Control/Status register bits
D15
D7
X
X
Symbol
X
PR5
PR4
PR3
X
PR1
PR0
X
REF
X
DAC
ADC
Rev. 02 — 21 June 2002
D14
D6
X
X
Type
R
RW
RW
RW
R
RW
RW
R
R
R
R
R
D13
PR5
D5
X
Description
Reserved.
Internal clock disable.
Digital interface (AC-link) power-down (external
clock off).
Audio V
Reserved.
Audio DAC and output path power-down.
Audio ADC and input path power-down.
Reserved.
Audio V
Reserved.
Audio DAC section ready to accept data.
Audio ADC section ready to transmit data.
Audio codec with touch screen controller
PR4
D12
D4
X
REF
REF
power-down.
up to nominal level.
PR3
REF
and power management monitor
D11
D3
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
D10
D2
X
X
UCB1400
DAC
PR1
D9
D1
ADC
PR0
38 of 63
D8
D0

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