mpc2107 Freescale Semiconductor, Inc, mpc2107 Datasheet - Page 14
mpc2107
Manufacturer Part Number
mpc2107
Description
256kb And 512kb Burstramtm Secondary Cache Mod
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC2107.pdf
(24 pages)
MPC2104 MPC2105 MPC2106 MPC2107
14
ASYNCHRONOUS DATA RAMs WRITE CYCLE 1
NOTES:
Write Cycle Time
Address Set–up Time
Address Valid to End of Write
Write Pulse Width
Write Pulse Width, G High
Data Valid to End of Write
Data Hold Time
Write Low to Output High–Z
Write High to Output Active
Write Recovery Time
1. A write occurs during the overlap of E low and W low.
2. If E goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If E
5. At any given voltage and temperature, t WLQZ (max) is less than t WHQX (min), both for a given device and from device to device.
6. Transition is measured 500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
W (WRITE ENABLE)
V IH , the output will remain in a high impedance state.
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
D (DATA IN)
ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
Parameter
HIGH–Z
t AVWL
t WLQZ
(See Notes 1 and 2)
t AVWH
t AVAV
Symbol
t WLWH
t WLWH
t DVWH
t WHDX
t WHQX
t AVWH
t WLEH
t WLEH
t WLQZ
t WHAX
t AVWL
t WLWH
t WLEH
t AVAV
t DVWH
DATA VALID
HIGH–Z
Min
15
12
12
10
0
7
0
0
5
0
MPC2107–15
t WHDX
Max
t WHQX
t WHAX
—
—
—
—
—
—
—
—
—
MOTOROLA FAST SRAM
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
5,6,7
5,6,7
3
4