mpc2107 Freescale Semiconductor, Inc, mpc2107 Datasheet

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mpc2107

Manufacturer Part Number
mpc2107
Description
256kb And 512kb Burstramtm Secondary Cache Mod
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
256KB and 512KB BurstRAM
Secondary Cache Modules for
PowerPC
cache for the PowerPC 60x microprocessor family in conformance with the
PowerPC Reference Platform (PReP) and the PowerPC Common Hardware
Reference Platform (CHRP) specifications. These products utilize synchronous or
asynchronous data RAMs.
The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182
(91 x 2) pin DIMM format. The MPC2104 uses four of Motorola’s 5 V 32K x 18;
the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the
5 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field
plus 16K x 2 for valid and dirty status bits is used.
generated internal to the BurstRAM by the CNTEN signal.
clock (CLKx) inputs. Eight write enables are provided for byte write control.
32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured
as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst
capability is provided in that two burst addresses bypass the address latch.
trol. A serial EEPROM is optional to provide more in–depth description of the
cache module. This EEPROM will be available on future revisions of the module
family.
path to lower voltage and power savings. Both power supplies must be connected.
BurstRAM is a trademark of Motorola.
PowerPC is a trademark of International Business Machines Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA FAST SRAM
11/8/95
The MPC2104/5/6/7 are designed to provide burstable, high performance L2
The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs.
Bursts can be initiated with the ADS signal. Subsequent burst addresses are
Write cycles are internally self timed and are initiated by the rising edge of the
The MPC2107 utilizes asynchronous data RAMs. The module is configured as
Presence detect pins are available for auto configuration of the cache con-
The module family pinout will support 5 V and 3.3 V components for a clear
All of these cache modules are plug and pin compatible with each other.
Motorola, Inc. 1995
PowerPC–style Burst Counter on Chip (MPC2104/5/6)
Flow–Through Data I/O (MPC2104/5/6)
Plug and Pin Compatibility of entire Module Family
Multiple Clock Pins for Reduced Loading
All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible (MPC2104/5/6)
Three State Outputs
Byte Write Capability
Fast Module Clock Rates: Up to 66 MHz
Fast SRAM Access Times: 10 ns for Tag RAM Match
Decoupling Capacitors for Each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
182 Pin Card Edge Module
Burndy Connector, Part Number: ELF182JSC–3Z50
PReP/CHRP Platforms
15 ns for Data RAM (MPC2107)
9 ns for Data RAM (MPC2104/5/6)
MPC2104 MPC2105 MPC2106 MPC2107
MPC2104
MPC2105
MPC2106
MPC2107
Order this document
by MPC2104/D
1

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mpc2107 Summary of contents

Page 1

... Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. The MPC2107 utilizes asynchronous data RAMs. The module is configured as 32K the same 182 pin DIMM format. Again cache tag RAMs configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used ...

Page 2

... TOP VIEW – CASE TBD NOTES and must be connected on all modules. MPC2104 MPC2105 MPC2106 MPC2107 PD1/IDSDATA PIN ASSIGNMENT PD3 DH31 182–LEAD DIMM DH29 DH27 DH25 CWE3 DH23 DH21 DH18 V SS DH16 CWE2 DH14 DH13 ...

Page 3

... A0 – A12 SFUNC, SG TDQ0 – TDQ10 TAG, TAD, E2 TDQ11 TAH, PWRDN RESET MATCH SW DIRTYQ TW V CCQ K VALIDQ VALIDD WTQ DIRTYD TG MPC2104 MPC2105 MPC2106 MPC2107 CLK3 = NC CLK0 CLK4 = NC ALE = NC DH0 – DH7 + DP0 ADS1 = NC DH8 – DH15 + DP1 CNTEN1 = NC CWE0 COE1 = NC CWE1 ...

Page 4

... BAA G E Note: All 64K X 18 TSP signals are tied via a 100 Ω resistor. Edge connector A28 connects to the 64K x 18 A0; edge connector A27 connects to the 64K x 18 A1. MPC2104 MPC2105 MPC2106 MPC2107 4 MPC2106 BLOCK DIAGRAM CLK0 K DH0 – DH7 + DP0 DQ0 – ...

Page 5

... DQ0 – DQ7 CWE5 W DL16 – DL23 DQ0 – DQ7 CWE6 DL24 – DL31 DQ0 – DQ7 CWE7 W MPC2104 MPC2105 MPC2106 MPC2107 X24C00 (OPTIONAL) PD1/IDSDATA SCL J2 SDA J3 TAG: 16K A13 A0 – A12 TT1, WTD TDQ0 – TDQ11 ...

Page 6

... Next to least significant address bit when asynchronous Data RAMs are used. Input Clock Inputs – CLK2 is for Tag RAM, CLK0 and 4 are for Data RAMs only. For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0–CLK2 only. For MPC2107 use CLK2 only. I/O High Data Bus – (MSB:0, LSB:31) I/O Low Data Bus – ...

Page 7

... T bias – + stg – 125 C MPC2104 MPC2105 MPC2106 MPC2107 Operation Deselected Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst I/O Status High– ...

Page 8

... MHz 3 Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Tag Output Capacitance Data RAM Input/Output Capacitance Tag Input/Output Capacitance MPC2104 MPC2105 MPC2106 MPC2107 8 5 Unless Otherwise Noted) (Voltages referenced ns) for I 20.0 mA. ...

Page 9

... Address Advance t BAVVKH Chip Enable t EVKH Address t KHAX Address Status t KHTSX Data In t KHDX Write t KHWX Address Advance t KHBAX Chip Enable t KHEX MPC2104 MPC2105 MPC2106 MPC2107 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V See Figure 1A Unless Otherwise Noted MPC2104 MPC2105 MPC2106 Min Max Unit Notes 15 — ns — — ...

Page 10

... DATA OUT NOTES: 1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with A2 as the base address. ...

Page 11

... A(12, 13 – 26) CWE0 – CWE7 STANDBY CNTEN0 DATA IN SINGLE WRITE NOTES: 1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106. 2. COE0 = V IH MOTOROLA FAST SRAM t KHKL t SVKH t KHTSX t AVKH t KHAX A2 t WVKH t EVKH ...

Page 12

... Transition is measured 500 mV from steady–state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected ( COE0 = Applies to MPC2107. MPC2104 MPC2105 MPC2106 MPC2107 Unless Otherwise Noted) 1.5 V Output Timing Reference Level ...

Page 13

... G (OUTPUT ENABLE) HIGH–Z Q (DATA OUT) t ELICCH V CC SUPPLY CURRENT MOTOROLA FAST SRAM (See Note 7) t AVAV t AXQX t AVQV (See Note 3) t AVAV t AVQV t ELQV t ELQX t GLQV t GLQX MPC2104 MPC2105 MPC2106 MPC2107 DATA VALID t EHQZ t GHQZ HIGH–Z DATA VALID t EHICCL 13 ...

Page 14

... Transition is measured 500 mV from steady–state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) HIGH–Z Q (DATA OUT) MPC2104 MPC2105 MPC2106 MPC2107 14 (See Notes 1 and 2) Symbol t AVAV t AVWL t AVWH t WLWH t WLEH ...

Page 15

... AVEH 12 t ELEH 10 t ELWH t DVEH 7 t EHDX 0 t EHAX 0 t AVAV t AVEH t ELEH t AVEL t ELWH t WLEH t DVEH DATA VALID HIGH–Z MPC2104 MPC2105 MPC2106 MPC2107 Max Unit Notes — — ns — ns — — ns — ns — EHAX ...

Page 16

... M = high if TAG IN equals the memory contents at the address low if TAG IN does not equal the ocntents at that address. 3. PWRDN and RESET are high for this table. OES and CLK are X. 4. This column represents the stored memory cell data for the given status bit at the selected address. MPC2104 MPC2105 MPC2106 MPC2107 16 TAG RAM ...

Page 17

... Symbol Min t KHKH 15 t KHKL 4.5 t KLKH 4.5 t KHQX 1.5 Address t AVKH 3 t WVKH Write Address t KHAX 1.5 t KHWX Write t KHSX 0 t KHSV — MPC2104 MPC2105 MPC2106 MPC2107 . . . . . . . . . . . . . 1.5 V Figure 1A Unless Otherwise Noted Tag RAM Max Unit Notes — — — ...

Page 18

... MPC2104 MPC2105 MPC2106 MPC2107 18 MOTOROLA FAST SRAM ...

Page 19

... AXMX t GLML t GHMX Symbol t STC t HTC t SRST t SHRS t RSML t RSMV t RSQZ t RSQX t PDSR t RHWX +5 V 480 Ω OUTPUT 255 Ω Figure 1B MPC2104 MPC2105 MPC2106 MPC2107 Tag RAM Min Max Unit Notes — — — — ns — — ...

Page 20

... MPC2104 MPC2105 MPC2106 MPC2107 20 MOTOROLA FAST SRAM ...

Page 21

... CLK t STC TCLR DIRTYOUT TWE MATCH t RSQZ* A0 – A11 * Transition is measured plus or minus 200 mV from steady state. MOTOROLA FAST SRAM TAG RAM TCLR FUNCTION t HTC t SRST t SHRS t RHWX t WVKH t RSMV t RSQX MPC2104 MPC2105 MPC2106 MPC2107 VALID 21 ...

Page 22

... Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc Equal Opportunity/Affirmative Action Employer. MPC2104 MPC2105 MPC2106 MPC2107 22 ORDERING INFORMATION (Order by Full Part Number) ...

Page 23

... MOTOROLA FAST SRAM MPC2104 MPC2105 MPC2106 MPC2107 23 ...

Page 24

... P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com MPC2104 MPC2105 MPC2106 MPC2107 24 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd. ...

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