at75c220 ATMEL Corporation, at75c220 Datasheet - Page 26
at75c220
Manufacturer Part Number
at75c220
Description
Smart Internet Appliance Processor Siap
Manufacturer
ATMEL Corporation
Datasheet
1.AT75C220.pdf
(144 pages)
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Figure 10. Read Showing a Single Access for a Non-sequential Read to a New Row
Writes can burst continuously until any of the following con-
ditions are achieved:
1. The following access is a read.
2. The following access is to a new row.
3. The following access is non-sequential.
When any of these conditions occur, the write burst is bro-
ken and SDMC goes inactive.
Table 11. SDRAM Refresh Rates
26
SDRAM CMD
sdmc_data
Clock Speed (MHz)
hburst_h
BTRAN
BWAIT
BCLK
Addr
BD
BA
0.0032
0.025
40
8
1
AT75C220
NSEQ
INCR
NOP
A0
BANK
PRE
NOP
Tick (us)
3125
0.25
1.25
400
10
ACT
ROW
SDRAM Refresh
Table 11 shows the counter values needed for a refresh
rate of 15.625 µs in the SDMC. As can be seen, at clock
speeds of 1 MHz and below it is unfeasible to maintain data
integrity in the SDRAM. Note that in low power modes it is
not a requirement to maintain data in the SDRAM.
NOP
NSEQ
INCR
A1
READ
COL0
COL1
NOP
Counter Needed
0.0390625
D0
1.5625
0.005
62.5
12.5
NOP
D0
NOP
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