at75c220 ATMEL Corporation, at75c220 Datasheet - Page 140
at75c220
Manufacturer Part Number
at75c220
Description
Smart Internet Appliance Processor Siap
Manufacturer
ATMEL Corporation
Datasheet
1.AT75C220.pdf
(144 pages)
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WD: Watchdog Timer
The AT75C220 has an internal watchdog timer which can
be used to prevent system lock-up if the software becomes
trapped in a deadlock. In normal operation, the user
reloads the watchdog at regular intervals before the timer
overflow occurs. If an overflow does occur, the watchdog
timer generates one or a combination of the following sig-
nals depending on the parameters in WD_OMR:
•
•
•
Figure 34. Watchdog Timer Block Diagram
WD User Interface
WD Base Address: 0xFF028000
140
If RSTEN is set, an internal reset is generated
(WD_RESET as shown in Figure 34).
If IRQEN is set, a pulse is generated on the signal
WDIRQ which is connected to the advanced interrupt
controller
If EXTEN is set, a low level is driven on the NWDOVF
signal for a duration of eight ACLK cycles.
Offset
0x0C
0x00
0x04
0x08
ACLK/1024
ACLK/128
ACLK/32
ACLK/8
WD_RESET
Advanced
Bus (APB)
Peripheral
WDIRQ
Register Name
WD_OMR
WD_CMR
AT75C220
WD_CR
WD_SR
Register Description
Overflow Mode Register
Clock Mode Register
Control Register
Status Register
Clock Select
Control Logic
CLK_CNT
The watchdog timer has a 16-bit down counter. Bits 12 - 15
of the value loaded when the watchdog is restarted are pro-
grammable using the HPCV parameter in WD_CMR. Four
clock sources are available to the watchdog counter:
ACLK/8, ACLK/32, ACLK/128 or ACLK/1024. The selection
is made using the WDCLKS parameter in WD_CMR. This
provides a programmable time-out period of 1.3 ms to 2.6
seconds with a 24 MHz system clock.
All write accesses are protected by control access keys to
help prevent corruption of the watchdog should an error
condition occur. To update the contents of the mode and
control registers, it is necessary to write the correct bit pat-
tern to the control access key bits at the same time as the
control bits are written (the same write access).
Clear
Overflow
Programmable
Down Counter
16-Bit
Read/write
Read/write
Read-only
Write-only
Access
NWDOVF
Reset Value
0
0
–
0
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