gc80c590ae CORERIVER Semiconductor, gc80c590ae Datasheet - Page 48

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gc80c590ae

Manufacturer Part Number
gc80c590ae
Description
Flash / Isp / Iap 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
SCON1 (B1h) : Serial Port Control Register for UART1
6.9. UART : UART1 SFRs
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
SM0
SM0, SM1 : Serial Port Operating Mode Selection
SM2 : Enable the Automatic Address Recognition in Mode 2 and 3.
REN : Enable/Disable Reception.
TB8
RB8
TI
RI
: 9th data bit that will be transmitted in Mode 2 and 3.
: 9th data bit that was received in Mode 2 and 3.
: Transmission Interrupt Flag. Must be cleared by S/W.
: Reception Interrupt Flag. Must be cleared by S/W.
SM1
Clear after receiving the address.
In Mode 1, the Validity of the Stop Bit is checked if SM2=1.
In Mode 0, SM2 should be 0.
In Mode 1, RB8 is equal to Stop Bit if SM2=0.
In Mode 0, RB8 is not used.
[0,0] : Mode 0. 8-bit Shift Register (OSC/4)
[0,1] : Mode 1. 8-bit UART (Variable)
[1,0] : Mode 2. 9-bit UART (OSC/32 or OSC/16)
[1,1] : Mode 3. 9-bit UART (Variable)
SM2
Semiconductor Co., Ltd.
REN
TB8
RB8
TI
RI
SBUF1 (A1h) : Serial Data Buffer for UART1
SADDR1.7 SADDR1.6 SADDR1.5 SADDR1.4 SADDR1.3 SADDR1.2 SADDR1.1 SADDR1.0
SADEN1.7 SADEN1.6 SADEN1.5 SADEN1.4 SADEN1.3 SADEN1.2 SADEN1.1 SADEN1.0
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
SADDR1(AAh) : Slave Address Register of UART1
SADEN1(ABh) : Slave Address Mask Enable Register of UART1
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
Transmission buffer and reception buffer are separated.
Read and Write address are same.
or broadcast address assigned to serial port1.
Programmed with the given
MiDAS2.0 Family
[48]

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