spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 30

• Manufacturer Part Number: spc560p50l3
• Description: 32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
• Manufacturer: STMicroelectronics

Revision history
7
Table 5.
30/31
16-May-2009
12-Nov-2009
27-Nov-2009
27-Feb-2009
13-Jun-2009
Date
Revision history
Document revision history
Revision
1
2
3
4
5
Initial release.
Added 64-pin in pin muxing, pin mapping and mechanical data.
Removed 64-pin, changed the contents and added new RPNs.
Formatting and style corrections.
Revised the document to reflect the correct information on the two available
devices (with 384 KB and 512 KB flash memory).
Replaced erroneous 60 MHz core speed with 64 MHz core speed.
In the DSPI section, changed the number of chip selects (was up to 4, is up
to 8).
Added the commercial product code structure.
Removed the feature list (in Section 3.2).
Added a revision history.
Editorial changes.
In the block diagram:
– Removed the Nexus block from the core.
– Moved the JTAG block to outside the core.
– Move the ECSM block.
In the device comparison table:
– Added entries for Safety Channel and Data Flash
– Changed the flash memory information to indicate only the program flash
– Added “Full Feature“ and “Airbag“ customization.
In the feature list:
– Replaced “32-bit Power Architecture Book E CPU” with “32-bit Power
– Specified LIN 2.1 in communications interfaces feature.
– Updated “Available memory” sub-bullet to “As much as 512 KB on-chip
– Changed ADC sub-bullet to “Two × 15 input channels, four channels
In the feature details:
– In the ADC section, changed “TUE <1.5 LSB” to “TUE <3 LSB”.
– In the temperature sensor section, changed “Accuracy of the sensor ±5
– In the JTAG section, removed sentence “The size of the boundary scan
– In the CTU section, changed CTU queue bullet to “4 independent result
In the order codes table:
– Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash
– Replaced the value of RAM from 32 to 36KB in the last four rows.
memory
Architecture
code flash memory with additional 64 KB for EEPROM emulation (Data
Flash), with ECC, with erase/program controller”.
shared among the two A/D converters”.
°C (tbc)” to “Calibrated sensor accuracy ±5 °C”
register is parameterized to support a variety of boundary scan chain
lengths.”
queues (2 × 16 entries, 2 × 4 entries)”.
(EE) (KB)“.
Doc ID 13950 Rev 5
™
Book III-E CPU”.
Description
SPC560P44Lx, SPC560P50Lx