spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 23

• Manufacturer Part Number: spc560p50l3
• Description: 32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
• Manufacturer: STMicroelectronics

SPC560P44Lx, SPC560P50Lx
3.2.26
3.2.27
Digital part:
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Cross Triggering Unit (CTU)
The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests
on user selected conditions without CPU load during the PWM period and with minimized
CPU load for dynamic configuration.
It implements the following features:
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Junction temperature sensor
The SPC560Px has a junction temperature sensor for measuring, by the ADC, the
temperature of the silicon.
2 × 13 input channels
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Four analog watchdogs comparing ADC results against predefined levels (low, high,
range) before results are stored in the appropriate ADC result location,
2 modes of operation: normal mode or CTU control mode
Normal mode features
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CTU control mode features
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Double buffered trigger generation unit with up to eight independent triggers generated
from external triggers
Trigger generation unit configurable in sequential mode or in triggered mode
Each trigger can be appropriately delayed to compensate the delay of external low
pass filter
Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with up to 24 ADC commands
Each trigger has the capability to generate consecutive commands
ADC conversion command allows to control ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
Total of 26 channels includes 4 channels shared among the two converters
Register based interface with the CPU: control reg., status reg., 1 result register
per channel
ADC state machine managing 3 request flows: regular command, hardware
injected command, software injected command
Selectable priority between software and hardware injected commands
4 analog watchdogs comparing ADC results against predefined levels (low, high,
range)
DMA compatible interface
Triggered mode only
Four independent result queues (2 × 16 entries, 2 × 4 entries)
Result alignment circuitry (left justified; right justified)
32-bit read mode allows to have channel ID on one of the 16-bit part
DMA compatible interfaces
Doc ID 13950 Rev 5
Overview of the SPC560Px
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