spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 16

• Manufacturer Part Number: spc560p50l3
• Description: 32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
• Manufacturer: STMicroelectronics

Overview of the SPC560Px
3.2.13
3.2.14
3.2.15
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Software Watchdog Timer (SWT)
The SWT has the following features:
Fault Collection Unit (FCU)
The FCU provides an indipendent fault reporting mechanism even in case the CPU is
misbehaving.
The FCU module has the following features:
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System Integration Unit (SIU-Lite)
The SPC560Px SIU-Lite controls MCU pad configuration, external interrupt, General
Purpose I/O (GPIO) and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
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FCU status register reporting the device status
Continuous monitoring of critical fault signals
User selection of critical signals from different fault sources inside the device
Critical fault events trigger two external pins (user selected signal protocol) that can be
used externally to reset the device and/or other circuitry (ex: safety relay, FlexRay
transceiver)
Faults are latched into a register
Centralized General Purpose Input Output (GPIO) control of up to 82 input/output pins
and 26 analog input only pads (package dependent)
All GPIO pins can be independently configured to support pull-up, pull-down or no pull
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
All peripheral pins (except ADC channels) can be alternatively configured as both
general purpose input or output pins
ADC channels support alternative configuration as general purpose inputs
Direct readback of the pin value is supported on all pins through the SIU
Configurable digital input filter that can be applied to some general purpose input pins
for noise elimination
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32-bit time-out register to set the time-out period
Programmable selection of system or oscillator clock for timer operation
Programmable selection of window mode or regular servicing
Programmable selection of reset or interrupt on an initial time-out
Master access protection
Hard and soft configuration lock bits
Reset configuration inputs allow timer to be enabled out of reset
Up to four internal functions can be multiplexed onto 1 pin
Doc ID 13950 Rev 5
SPC560P44Lx, SPC560P50Lx