mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 93

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

22.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
in
Freescale Semiconductor
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Table 73
1
2
Core PLL Configuration
CFG_CLKIN_DIV
pulled down (low) in agent mode.
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
should be considered reserved.
0-1
nn
00
01
at reset
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
RCWL[COREPLL]
1
Table 73
0000
0001
0001
2-5
Table 72. CSB Frequency Options (continued)
shows the encodings for RCWL[COREPLL]. COREPLL values not listed
SPMF
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
Table 73. e300 Core PLL Configuration
6
n
0
0
(PLL off, csb_clk clocks core
Input Clock
core_clk : csb_clk Ratio
csb_clk :
Ratio
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
7 : 1
8 : 1
9 : 1
PLL bypassed
2
directly)
1:1
1:1
16.67
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
(PLL off, csb_clk clocks core
25
PLL bypassed
VCO divider
directly)
33.33
100
133
166
200
233
÷
÷
2
4
66.67
2
133
200
266
333
Clocking
93