mpc8343e Freescale Semiconductor, Inc, mpc8343e Datasheet - Page 62

• Manufacturer Part Number: mpc8343e
• Description: Mpc8343e Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

1
2
3
Clocking
Table 49
conditions.
19.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
62
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
DDR memory bus frequency (MCLK)
Local bus frequency (LCLK n )
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
USB_DR, USB_MPH maximum internal operating
frequency
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk , MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBIUCM]).
provides the operating frequencies for the MPC8343E PBGA under recommended operating
System PLL Configuration
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Characteristic
3
1
Table 50. System PLL Multiplication Factors
2
Table 49. Operating Frequencies for PBGA
RCWL[SPMF]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
266 MHz
200–266
System PLL Multiplication
Reserved
Factor
× 16
× 10
× 11
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
Table 50
16.67–133
333 MHz
200–333
100–266
100–133
25–66
133
133
shows the multiplication factor
Freescale Semiconductor
400 MHz
200–400
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit