mpc8343e Freescale Semiconductor, Inc, mpc8343e Datasheet - Page 19

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mpc8343e

Manufacturer Part Number
mpc8343e
Description
Mpc8343e Powerquicc
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Figure 6
Table 16
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Freescale Semiconductor
4 devices (12 pF)
9 devices (27 pF)
36 devices (108 pF) + 40 pF compensation capacitor
36 devices (108 pF) + 80 pF compensation capacitor
ADDR/CMD
MDQS[n]
shows the DDR SDRAM output timing diagram for source synchronous mode.
provides approximate delay information that can be expected for the address and command
MDQ[x]
MCK[n]
MCK[n]
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Figure 6. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 16. Expected Delays for Address/Command
Write A0
t
DDKHAS
t
DDKHDX
t
Load
MCK
,t
t
DDKHCS
DDKHAX
NOOP
D0
, t
t
DDKHCX
DDKHDS
t
t
DDKHMP
DDKHMH
D1
t
DDKLDS
t
DDKLDX
t
DDKHME
Delay
3.0
3.6
5.0
5.2
DDR SDRAM
Unit
ns
ns
ns
ns
19

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