mpc8343e Freescale Semiconductor, Inc, mpc8343e Datasheet - Page 17

• Manufacturer Part Number: mpc8343e
• Description: Mpc8343e Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
At recommended operating conditions with GV
MCS(n) output hold with respect to MCK
MCK to MDQS
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to
MDQS
MDQS preamble start
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the clock control register.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
5. Note that t
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8343E. Note that t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
For the skew measurements referenced for t
address/command valid with the rising edge of MCK.
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same
delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters
have been set to the same adjustment value. See the MPC8349E PowerQUICC™ II Pro Integrated Host Processor Family
Reference Manual , for a description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8343E.
conventions described in note 1.
DDKHAS
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
symbolizes DDR timing (DD) for the time t
DDKHMH
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
follows the symbol conventions described in note 1. For example, t
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
DD
of 2.5 V ± 5%.
DDKLDX
AOSKEW
Symbol
t
t
t
t
t
t
t
t
DDKHMH
DDKHDS,
DDKHDX,
DDKHMP
DDKHCX
DDKLDS
DDKLDX
DDKLME
MCK
symbolizes DDR timing (DD) for the time t
it is assumed that the clock adjustment is set to align the
memory clock reference (K) goes from the high (H) state until outputs
1
–0.25 × t
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. Output hold time can be read as DDR timing
1200
1200
2.65
–0.9
–1.1
–1.2
Min
900
900
900
900
-0.9
2.0
3.8
MCK
– 0.9
–0.25 × t
DDKHMH
DDKHMH
Max
0.3
0.5
0.6
0.3
—
—
—
MCK
can be modified through control
describes the DDR timing (DD)
MCK
+ 0.3
DDKHMP
memory clock reference
follows the symbol
Unit
ns
ns
ps
ps
ns
ns
DDR SDRAM
Notes
for
4
5
6
6
7
7
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