mpc8241tzq266c Freescale Semiconductor, Inc, mpc8241tzq266c Datasheet - Page 8

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mpc8241tzq266c

Manufacturer Part Number
mpc8241tzq266c
Description
Mpc8241 Integrated Processor Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Electrical and Thermal Characteristics
Figure 2
8
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in
2. See the Cautions section of
3. Refer to
4. Refer to
5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN
6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation
shows supply voltage sequencing and separation cautions.
clock cycle for the device to be in the nonreset state.
of HRST_CTRL and HRST_CPU negate in order to be latched.
3.3 V
5 V
2 V
0
Configuration Pins
Table 8
Table 10
HRST_CPU and
HRST_CTRL
Figure 2. Supply Voltage Sequencing and Separation Cautions
Power Supply Ramp Up
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
for details on PLL relock and reset signal assertion timing requirements.
for details on reset configuration pin setup timing requirements.
3
Reset
6
Table 2
6
V
5
Maximum Rise Time Must be Less Than
DD
for details on this topic.
5
Stable
One External Memory Clock Cycle
2
2
See Note 1
Clock Cycles Setup Time
Nine External Memory
Relock
100 µs
Time
PLL
3
External Memory
HRST_CPU and
Clock Cycles
HRST_CTRL
Asserted 255
LV
GV
V
DD
DD
DD
/AV
@ 5 V
_OV
4
DD
5
DD
/AV
/(LV
3
DD
2
DD
@ 3.3 V - - - -)
PLL
VM = 1.4 V
Table
Freescale Semiconductor
6
Time
2.

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