mc68hc11d0 Freescale Semiconductor, Inc, mc68hc11d0 Datasheet - Page 75

• Manufacturer Part Number: mc68hc11d0
• Description: Mc68hc11d0 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

TECHNICAL DATA
The prescale bits, SCP[1:0], determine the highest baud rate and the SCR[2:0] bits se-
lect an additional binary submultiple ( 1
rate. The result of these two dividers in series is the 16 X receiver baud rate clock. The
SCR[2:0] bits are not affected by reset and can be changed at any time, although they
should not be changed when any SCI transfer is in progress.
Figure 7-3 illustrates the SCI baud rate timing chain. The prescale select bits deter-
mine the highest baud rate. The rate select bits determine additional divide by two
stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result
of dividing the RT clock by 16.
SCR[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
Prescaler
Divide
Table 7-2 Baud Rate Selects
128
By
16
32
64
1
2
4
8
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(Prescaler Output from Previous Table)
4800
4800
2400
1200
600
300
150
—
—
2, 4 through 128) of this highest baud
Highest Baud Rate
9600
9600
4800
2400
1200
600
300
150
—
38.4 K
38.4 K
19.2 K
9600
4800
2400
1200
600
300
7-9