mc68hc11d0 Freescale Semiconductor, Inc, mc68hc11d0 Datasheet - Page 53

• Manufacturer Part Number: mc68hc11d0
• Description: Mc68hc11d0 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.4.1 Interrupt Recognition and Register Stacking
TECHNICAL DATA
An interrupt can be recognized at any time after it is enabled by its local mask, if any,
and by the global mask bit in the CCR. Once an interrupt source is recognized, the
CPU responds at the completion of the instruction being executed. Interrupt latency
varies according to the number of cycles required to complete the current instruction.
When the CPU begins to service an interrupt, the contents of the CPU registers are
pushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked,
the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The inter-
rupt vector for the highest priority pending source is fetched, and execution continues
at the address specified by the vector. At the end of the interrupt service routine, the
return from interrupt instruction is executed and the saved registers are pulled from the
stack in reverse order so that normal program execution can resume. Refer to SEC-
TION 3 CENTRAL PROCESSING UNIT for further information.
FFC0, C1 — FFD4, D5
Vector Address
FFDC, DD
FFDA, DB
FFEC, ED
FFDE, DF
FFEA, EB
FFFC, FD
FFD6, D7
FFD8, D9
FFEE, EF
FFFA, FB
FFFE, FF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
Table 5-4 Interrupt and Reset Vector Assignments
Freescale Semiconductor, Inc.
For More Information On This Product,
Real Time Interrupt
IRQ (External Pin)
XIRQ Pin
Software Interrupt
Illegal Opcode Trap
COP Failure
Reserved
SCI Serial System
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Clock Monitor Fail
RESET
SCI Transmit Complete
SCI Transmit Data Register Empty
SCI Idle Line Detect
SCI Receiver Overrun
SCI Receive Data Register Full
RESETS AND INTERRUPTS
Go to: www.freescale.com
Interrupt Source
CCR Mask
None
None
None
None
None
X Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
—
NOCOP
PAOVI
I4/O5I
Local
Mask
OC4I
OC3I
OC2I
OC1I
None
None
None
None
None
TCIE
SPIE
CME
ILIE
PAII
IC3I
IC2I
IC1I
RTII
RIE
RIE
TOI
TIE
—
—
5-9