mc68hc11d0 Freescale Semiconductor, Inc, mc68hc11d0 Datasheet - Page 21

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mc68hc11d0

Manufacturer Part Number
mc68hc11d0
Description
Mc68hc11d0 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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3.1 CPU Registers
TECHNICAL DATA
This section presents information on M68HC11 central processing unit (CPU) archi-
tecture, data types, addressing modes, the instruction set, and special operations,
such as subroutine calls and interrupts.
The CPU is designed to treat all peripheral, I/O, and memory locations identically as
addresses in the 64 Kbyte memory map. This is referred to as memory-mapped I/O.
There are no special instructions for I/O that are separate from those used for memory.
This architecture also allows accessing an operand from an external memory location
with no execution-time penalty.
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if
they were memory locations. The seven registers, discussed in the following para-
graphs, are shown in Figure 3-1.
15
7
A
Freescale Semiconductor, Inc.
CENTRAL PROCESSING UNIT
For More Information On This Product,
Figure 3-1 Programming Model
0
SP
PC
D
IX
IY
CENTRAL PROCESSING UNIT
7
7
S
Go to: www.freescale.com
X
SECTION 3
H
I
B
N
Z
V
C
0
0
0
8-BIT ACCUMULATORS A & B
OR 16-BIT DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
CONDITION CODES
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
HC11 PROG MODEL
3-1

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