mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 70
mc68hc05ct4fn
Manufacturer Part Number
mc68hc05ct4fn
Description
Mc68hc05 Family Of Microcontrollers Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC05CT4FN.pdf
(142 pages)
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Synchronous Serial Interface (SSI)
General Release Specification
SSI STATUS REG.
0 0 0 0 0 0
CLOCK GENERATOR
CONTROLS/ADDRESS BUS
Transmission in master mode is initiated by a write to the SSI data
register (SDR). A transfer cannot be initiated in slave mode; the external
master initiates the transfer. The programmer must choose between
master or slave mode before the SSI is enabled. The programmer must
ensure that only one master exists in the system at any one time. All
devices in the system must operate with the same clock polarity and
data rates. Slaves should always be disabled before the master is
disabled.
Freescale Semiconductor, Inc.
SSI CONTROL REG.
For More Information On This Product,
CONTROL LOGIC
Figure 9-1. SSI Block Diagram
Synchronous Serial Interface (SSI)
Go to: www.freescale.com
LSBF
MCU INTERNAL BUS
SSI DATA REG.
MSTR
SE
DATA BUS
&
HFF
TO INTERRUPT LOGIC
INTERRUPT CIRCUIT
MC68HC05CT4
—
Rev. 2.0
SCK
SDIO
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