mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 52
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mc68hc05ct4fn
Manufacturer Part Number
mc68hc05ct4fn
Description
Mc68hc05 Family Of Microcontrollers Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC05CT4FN.pdf
(142 pages)
- Current page: 52 of 142
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Operating Modes
6.4.4 Low-Power Wait
General Release Specification
NOTES:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
INTERNAL
INTERNAL
ADDRESS
CLOCK
RESET
OSC1 1
IRQ
IRQ
BUS
2
3
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
When the wait mode is entered by executing the WAIT instruction, the
oscillator divider changes from a divide-by-5 to a divide-by-40 (additional
divide-by-8) to lower the wait current. As a result, this gives a CPU clock
rate of 256 kHz if the oscillator is running with a 10.24-MHz crystal. The
oscillator divide-by-5 or divide-by-40 option is also controlled by the
speed bit located in the miscellaneous control register ($21).
Section 14. Miscellaneous
via an interrupt, the OSC rate prior to entering wait mode is restored.
Figure 6-2. Stop Recovery Timing Diagram
Freescale Semiconductor, Inc.
t
t
RL
LIH
For More Information On This Product,
t ILCH
Go to: www.freescale.com
Operating Modes
1FFE
Register. When returning from wait mode
4064 t
cyc
1FFE
1FFE
RESET OR INTERRUPT
VECTOR FETCH
1FFE
MC68HC05CT4
1FFF
—
Rev. 2.0
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