mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 75

• Manufacturer Part Number: mc68hc908gp32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Bit7–Bit4 — Unimplemented Bits
5.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
MUL7–MUL0 — Multiplier Select Bits
5.5.5 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
VRS7–VRS0 — VCO Range Select Bits
Freescale Semiconductor
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
These bits have no function and always read as logic 0s.
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (See
hardware center-of-range frequency, f
5.3.3 PLL
Address:
Address:
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
PMRS may be called PVRS on other HC08 derivatives.
Reset:
Reset:
Read:
Read:
Write:
Write:
Circuits,
$003A
$0038
Figure 5-7. PLL Multiplier Select Register Low (PMSL)
MUL7
VRS7
Bit 7
Bit 7
Figure 5-8. PLL VCO Range Select Register (PMRS)
0
0
5.3.6 Programming the
5.3.3 PLL Circuits
MUL6
VRS6
6
1
6
1
MC68HC908GP32 Data Sheet, Rev. 10
MUL5
VRS5
VRS
5
0
5
0
. VRS7–VRS0 cannot be written when the PLLON bit in the
NOTE
NOTE
NOTE
and
MUL4
VRS4
4
0
4
0
PLL, and
5.3.6 Programming the
MUL3
VRS3
3
0
3
0
5.5.1 PLL Control
MUL2
VRS2
2
0
2
0
MUL1
VRS1
PLL.) MUL7–MUL0 cannot
1
0
1
0
Register.), controls the
MUL0
VRS0
Bit 0
Bit 0
0
0
CGM Registers
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