mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 145
mc68hc908gp32
Manufacturer Part Number
mc68hc908gp32
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908GP32.pdf
(266 pages)
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13.7.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with
port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit
in data direction register E (DDRE).
13.8 I/O Registers
These I/O registers control and monitor SCI operation:
13.8.1 SCI Control Register 1
SCI control register 1:
LOOPS — Loop Mode Select Bit
ENSCI — Enable SCI Bit
Freescale Semiconductor
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This read/write bit enables loop mode operation. In loop mode the PTE1/RxD pin is disconnected from
the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = Loop mode enabled
0 = Normal operation enabled
1 = SCI enabled
0 = SCI disabled
SCI control register 1 (SCC1)
SCI control register 2 (SCC2)
SCI control register 3 (SCC3)
SCI status register 1 (SCS1)
SCI status register 2 (SCS2)
SCI data register (SCDR)
SCI baud rate register (SCBR)
Enables loop mode operation
Enables the SCI
Controls output polarity
Controls character length
Controls SCI wakeup method
Controls idle character detection
Enables parity function
Controls parity type
Address:
Reset:
Read:
Write:
LOOPS
$0013
Bit 7
0
Figure 13-9. SCI Control Register 1 (SCC1)
ENSCI
6
0
MC68HC908GP32 Data Sheet, Rev. 10
TXINV
5
0
M
4
0
WAKE
3
0
ILTY
2
0
PEN
1
0
Bit 0
PTY
0
I/O Registers
145
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