mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 151

• Manufacturer Part Number: mc68hc908gp32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

OR — Receiver Overrun Bit
NF — Receiver Noise Flag Bit
Freescale Semiconductor
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence.
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD pin. NF generates an
SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1
and then reading the SCDR. Reset clears the NF bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
1 = Noise detected
0 = No noise detected
Figure 13-13
shows the normal flag-clearing sequence and an example of an overrun
MC68HC908GP32 Data Sheet, Rev. 10
I/O Registers
151