mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 213

• Manufacturer Part Number: mc68hc908gr16
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

16.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
The SPI status and control register also contains bits that perform these functions:
SPRF — SPI Receiver Full Bit
ERRIE — Error Interrupt Enable Bit
OVRF — Overflow Bit
MODF — Mode Fault Bit
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This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register.
Reset clears the SPRF bit.
This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears
the ERRIE bit.
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register. Reset clears the
OVRF bit.
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with
the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the
1 = Receive data register full
0 = Receive data register not full
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
1 = Overflow
0 = No overflow
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Address: $0011
Reset:
Read:
Write:
Figure 16-15. SPI Status and Control Register (SPSCR)
SPRF
Bit 7
0
= Unimplemented
ERRIE
6
0
MC68HC908GR16 Data Sheet, Rev. 5.0
OVRF
5
0
MODF
4
0
SPTE
3
1
MODFEN
2
0
SPR1
1
0
SPR0
Bit 0
0
I/O Registers
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