mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 212

no-image

mc68hc908gr16

Manufacturer Part Number
mc68hc908gr16
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc68hc908gr16CFA
Manufacturer:
FREESCALE
Quantity:
2 650
Part Number:
mc68hc908gr16CFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc908gr16CFA
Manufacturer:
FREESCALE
Quantity:
2 650
Part Number:
mc68hc908gr16CFA
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc68hc908gr16CFJ
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc908gr16MFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Peripheral Interface (SPI) Module
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable
SPTIE— SPI Transmit Interrupt Enable
212
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
16-5
CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
16-5
CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to 1 between bytes.
(See
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See
Resetting the
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
and
and
Figure
Figure
Figure
Address: $0010
16-13.) Reset sets the CPHA bit.
Reset:
Read:
Write:
SPI.) Reset clears the SPE bit.
16-7.) To transmit data between SPI modules, the SPI modules must have identical
16-7.) To transmit data between SPI modules, the SPI modules must have identical
SPRIE
Bit 7
R
0
Figure 16-14. SPI Control Register (SPCR)
= Reserved
R
6
0
MC68HC908GR16 Data Sheet, Rev. 5.0
SPMSTR
5
1
CPOL
4
0
CPHA
3
1
= Unimplemented
SPWOM
2
0
SPE
1
0
Freescale Semiconductor
SPTIE
Bit 0
0
Figure
Figure
16.9

Related parts for mc68hc908gr16