at43101 ATMEL Corporation, at43101 Datasheet - Page 5

• Manufacturer Part Number: at43101
• Description: Pcmcia Card Memory Interface Circuit With 256 Bytes Of Internal Attribute Memory Eeprom
• Manufacturer: ATMEL Corporation

Address Decoder Operation
Byte Control Logic Operation
The AT43101 provides separate output and write enables for
the upper and lower bytes of the memory array to implement
byte addressing. The assertion of these outputs under the
The IWP* input provides write protection for common
memory. When IWP* is low, assertion of IWEL* and
IWEH* is inhibited. The WPATT input provides write pro-
tection for the attribute memory when high. This signal is
pulled down internally for applications not requiring write
OE*
SEL[1:0]
H
H
H
H
H
H
L
L
L
L
L
XX
XX
XX
XX
XX
XX
XX
XX
WE*
H
H
H
H
H
H
L
L
L
L
L
SGL/DBL* = H
DEC[2:0]
HHH
LHH
HLH
HHL
LLH
LHL
HLL
LLL
CE2*
H
H
H
H
H
H
X
L
L
L
L
HHHHHHHL
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHHLHHHH
HHLHHHHH
HLHHHHHH
LHHHHHHH
CE1*
ICE[7:0]*
X
H
H
H
H
L
L
L
L
L
L
A0
X
X
H
X
X
X
H
X
X
L
L
control of A0, CE2*, CE1*, OE* and WE* is given by the
following table when REG* is high.
protection. In addition, the AT43101 is disabled for 3 milli-
seconds during power up to prevent writes from occurring
to either attribute or common memory. The state of the
A*/B pin is also latched at this time. The AT43101 does
not support the optional PCMCIA WAIT* signal.
SEL[1:0]
HH
LH
HL
LL
LL
LL
LL
IOEL*
H
H
H
H
H
H
H
H
H
L
L
SGL/DBL* = L
IOEH*
DEC[2:0]
H
H
H
H
H
H
H
H
L
L
L
AT43101
XHH
XXX
XXX
XXX
XLH
XHL
XLL
IWEL*
H
H
H
H
H
H
H
H
H
L
L
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHLHHHHH
HLHHHHHH
LHHHHHHH
HHHHHHHL
ICE[7:0]*
IWEH*
H
H
H
H
H
H
H
H
L
L
L
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