at43101 ATMEL Corporation, at43101 Datasheet
at43101
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at43101 Summary of contents
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... ROM OTP Description The AT43101 is a low power, high integration PCMCIA interface chip set for memory cards. It provides a complete PCMCIA PC Card Standard Release 2.1 compliant inter- face with no other support devices. Two AT43101’s are used on each memory card. A mode select pin configures the device for operation as a low order address and data buffer when low and as the high order address buffer/decoder when high ...
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... Pin Configuration AT43101 pins are defined by the following two tables. The Pin Descriptions Table lists and describes the function of each signal used in the chip set. The Pin Assignment Table lists the signals connected to each pin for each mode and the buffer type implemented for the corresponding pin. The ...
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... AT43101 Physical Pin Assignments Pkg Pin Mode A Mode B 1 OE* A10 2 D1 A11 3 D9 A17 4 D2 A18 5 D10 A19 6 D3 A20 7 D11 A21 8 VSS VSS 9 D4 SEL0 pu 10 D12 11 D5 A13 12 D13 A14 13 D6 A16 14 D14 A15 15 D7 A12 16 D15 A22 17 Reset pd ...
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... Both PCMCIA signals and memory devices connect directly to the AT43101 with no additional components required. The AT43101 acts as a data and address buffer and address and control signal decoder for both an external memory array and an internal 256x8 E2PROM which contains the Card Infor- mation Structure ...
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... X H protection. In addition, the AT43101 is disabled for 3 milli- seconds during power up to prevent writes from occurring to either attribute or common memory. The state of the A*/B pin is also latched at this time. The AT43101 does not support the optional PCMCIA WAIT* signal. AT43101 SGL/DBL DEC[2:0] ...
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... Attribute Memory accesses. During word accesses of Common Memory, D[15:0] and ID[15:0] are active. During byte accesses (other than Odd Byte Only accesses), the PCMCIA transfers take place on D[7:0] and the AT43101 performs the required byte lane swapping based and from D[15:8] or D[7:0] ADDRESS BUFFER ...
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... gered by the rising edge of the first of WE* or CE1 high. Writes to the E2PROM Attribute Memory must observe either a 10 ms. write recovery/cycle time or wait until R/B* goes inactive before another write can be initiated. AT43101 OE* WE* D[15:8] D[7: High Z High High Z ...
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... WE* CE1* CE2* REG* OE* A0 Absolute Maximum Ratings* Operating Temperature ........................ +70 C Storage Temperature ..................... - +150 C Voltage on Any Pin With Respect to VSS .................-0 Vcc +0.6 V Maximum Operating Voltage ............................ 6.1 V AT43101 8 ENB ENB Write Protect 256 X 8 EEPROM CE WE Ready/Busy* ADDR OE CONTROL LOGIC *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” ...
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... CC I out=0mA V =5.5 V Inputs out=0mA V =5.5 V Inputs out=0mA AT43101 Conditions Vin = 0 V Vout = 0 V AT43101 4 5.5 V Min Max Units - - -150 +150 A 200 0. ...
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... Symmetrical for assertion and de-assertion. Also applies to write cycles. 5. Not shown in timing diagram. Input Test Waveforms and Measurement Level MEASUREMENT LEVEL VDD <5 ns, test load capacitance is R1 ƒ AT43101 10 50pf Min Max Notes 250 ...
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... AC Read Waveforms A[24:0], SGL/DBL*, DEC[2:0], SEL[1:0] tia(A) IA[24:0] ICE[7:0]* REG* CE1*, CE2* OE* D[15:0] IOEH*, IOEL* ID[15:0] ADDRESS VALID tice(A) tice(REG) tice(CE) tda(A) ten(REG) ten(CE) ten(OE) HIGH Z tioel(CE) tioel(OE) tioel(REG) tioel(A0) td(ID) DATA VALID AT43101 tv(A) tioeh(AO) tdis(REG) tdis(CE) tdis(OE) DATA VALID tioeh(REG) tioeh(CE) tioeh(OE) 11 ...
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... Either or both of CE1*, CE2* assert according to function truth table. 3. REG* asserted only for Attribute Memory write. REG* must be stable during the write at the level appropriate to the memory type being accessed. 4. One or both of IWEH*, IWEL* assert per A0, CE1*, CE2*, provided REG* is high. 5. Not shown in timing diagrams. AT43101 12 2 PROM write 2 PROM ...
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... A. C. Write Waveforms - WE* Control A[24:0] tia(A) IA[24:0] D[15:0] ID[15:0] tsu(A) WE* CE1*, CE2* REG* tiwel(REG) tiwel(A0) IWEH*, IWEL* Ready/Busy* Waveforms WE* 1 R/B* 1) CE* or WE* dependant on controlling signal IR/B* R/B* ADDRESS VALID DATA VALID tsu(D) tid(D) twr tiwel(WE) tsu(CE) tsu(REG) tiwel(CE) t (WE) RB twc AT43101 th(A) tiweh(A0) th(D) tiweh(WE) th(CE) tiweh(CE) th(REG) tiweh(REG) t (IRB ...
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... ID[15:0] tsu(A) CE1*, CE2* tiwel(WE) WE* REG* tiwel(REG) tiwel(A0) IWEH*, IWEL* Packaging and Ordering Information Package Type TQFP AT43101 14 ADDRESS VALID th(A) DATA VALID tsu(D) th(D) twr tsu(CE) th(CE) tsu(REG) th(REG) tiwel(CE) tiweh(CE) Pin Count, Dimensions 64 pins thick tiweh(A0) tiweh(WE) tiweh(REG) Part Number AT43101 ...