at43101 ATMEL Corporation, at43101 Datasheet - Page 10

• Manufacturer Part Number: at43101
• Description: Pcmcia Card Memory Interface Circuit With 256 Bytes Of Internal Attribute Memory Eeprom
• Manufacturer: ATMEL Corporation

Notes:
AC Read Characteristics
Input Test Waveforms and Measurement Level
10
Symbol
tia(A)
tda(A)
ten(CE)
ten(OE)
ten(REG)
tdis(CE)
tdis(OE)
tdis(REG)
tioel(A0)
tioel(CE)
tioel(OE)
tioel(REG)
tioeh(A0)
tioeh(CE)
tioeh(OE)
tioeh(REG)
tv(A)
td(ID)
tice(A)
tice(REG)
tice(CE)
Ten (reset)
Tdis (reset)
V
0V
DD
t
VDD/2
R1
1. Either or both of CE1*, CE2* assert according to function truth table.
2. REG* asserted only for Attribute Memory read.
3. tda(A) applies to Attribute Memory read. Access time for Common Memory
4. Symmetrical for assertion and de-assertion. Also applies to write cycles.
5. Not shown in timing diagram.
t
ƒ
<5 ns, test load capacitance is
read is derived from tia(A), td(ID), and external device access time.
Parameter
Data access time, from A[8:0] to D[7:0]
Output enable time from CE*
Output enable time from OE*
Output enable time from REG*
Output disable time from OE*
Delay to data change, from change of address
Delay from ID[15:0] to D[15:0]
Delay to ICE[7:0]* from DEC[2:0], SEL[1:0], SGL/DBL*
Chip active enable time from reset
Chip active disable time from reset
Delay to IA[24:0], from A[24:0]
Output disable time from CE*
Output disable time from REG*
Delay to IOEL*, IOEH* assertion from A0
Delay to IOEL*, IOEH* assertion from CE*
Delay to IOEL*, IOEH* assertion from OE*
Delay to IOEL*, IOEH* assertion from REG*
Delay to IOEL*, IOEH* de-assertion from A0
Delay to IOEL*, IOEH* de-assertion from CE*
Delay to IOEL*, IOEH* de-assertion from OE*
Delay to IOEL*, IOEH* de-assertion from REG*
Delay to ICE[7:0]* from REG*
Delay to ICE[7:0]* from CE1*, CE2*
AC MEASUREMENT LEVEL
AT43101
50pf
0 ns
5 ns
5 ns
0 ns
Min
250 ns
30 ns
36 ns
36 ns
36 ns
58 ns
58 ns
58 ns
28 ns
28 ns
25 ns
28 ns
28 ns
28 ns
25 ns
28 ns
27 ns
38 ns
30 ns
50 ns
50 ns
38 ns
Max
Notes
3
1
2
1
1
2
1
2
4
4
5
5
4