cy8c5246pvi-092 Cypress Semiconductor Corporation., cy8c5246pvi-092 Datasheet - Page 32

• Manufacturer Part Number: cy8c5246pvi-092
• Description: Programmable System-on-chip Psoc
• Manufacturer: Cypress Semiconductor Corporation.

external voltage routed through an Extref pin is used to generate
the reference.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from Vddio. The
reference sets the pins voltage threshold for a high logic level.
Available input thresholds are:
Typically, an external voltage routed through an Extref pin
generates the Vref reference.
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
The digital input path in
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage (Vddio < Vin < Vdda)
tolerance feature at any operating Vdd.
A common application for this feature is connection to a bus such
as I
Document Number: 001-55034 Rev. *A
0.5 × Vddio
0.4 × Vddio
0.5 × Vref
Vref
There are no current limitations for the SIO pins as they present
a high impedance load to the external circuit.
The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the Vddio supply.
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the Vddio supply
voltage to which the GPIO belongs.
2
C where different devices are running from different supply
Figure 6-7
on page 29 illustrates this
Adjustable Input Level
PRELIMINARY
voltages. In the I
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull up to pull the I
supply. For example, the PSoC chip could operate at 1.8V, and
an external device could run from 5V. Note that the SIO pin’s VIH
and VIL levels are determined by the associated Vddio supply
pin.
The I/O pin must be configured into a high impedance drive
mode, open drain low drive mode, or pull down drive mode, for
over voltage tolerance to work properly. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
By default all I/Os reset to the High Impedance Analog state but
are reprogrammable on a port-by-port basis. They can be reset
as High Impedance Analog, Pull Down, or Pull Up, based on the
application’s requirements. To ensure correct reset operation,
the port reset configuration data is stored in special nonvolatile
registers. The stored reset data is automatically transferred to
the port reset configuration registers at PPOR release.
6.4.17 Low Power Functionality
In all low power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low power modes.
6.4.18 Special Pin Functionality
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in
features are:
6.4.19 JTAG Boundary Scan
The device supports standard JTAG boundary scan chains on all
pins for board level test.
7. Digital Subsystem
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture.
Designers do not need to interact directly with the programmable
digital system at the hardware and register level. PSoC Creator
Digital
Analog
4 to 33 MHz crystal oscillator
32.768 kHz crystal oscillator
Wake from sleep on I
for I
JTAG interface pins
SWD interface pins
SWV interface pins
External reset
External reference inputs
PSoC
2
C if wake from sleep is not required.
®
5: CY8C52 Family Data Sheet
2
C case, the PSoC chip is configured into the
2
C address match. Any pin can be used
2
C bus voltage above the PSoC pin
“Pinouts”
on page 5. The special
Page 32 of 85
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