cy8c5246pvi-092 Cypress Semiconductor Corporation., cy8c5246pvi-092 Datasheet - Page 25

• Manufacturer Part Number: cy8c5246pvi-092
• Description: Programmable System-on-chip Psoc
• Manufacturer: Cypress Semiconductor Corporation.

6.3 Reset
CY8C52 has multiple internal and external reset sources
available. The reset sources are:
Figure 6-5. Resets
Document Number: 001-55034 Rev. *A
Reset
Pin
Power source monitoring - The analog and digital power
voltages, Vdda, Vddd, Vcca, and Vccd are monitored in several
different modes during power up, normal operation, and sleep
and hibernate states. If any of the voltages goes outside prede-
termined ranges then a reset is generated. The monitors are
programmable to generate an interrupt to the processor under
certain conditions before reaching the reset thresholds.
External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull up to Vddio1. Vddd, Vdda, and Vddio1 must all
have voltage applied before the part comes out of reset.
Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
Software - The device can be reset under program control.
Vddd Vdda
Watchdog
Monitors
Software
External
Register
Voltage
Power
Reset
Timer
Reset
Level
Controller
Reset
PRELIMINARY
System
Processor
Reset
Interrupt
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power on reset.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
IPOR - Initial Power on Reset
At initial power on, IPOR monitors the power voltages Vddd
and Vdda, both directly at the pins and at the outputs of the
corresponding internal regulators. The trip level is not precise.
It is set to a voltage below the lowest specified operating volt-
age but high enough for the internal circuits to be reset and to
hold their reset state. The monitor generates a reset pulse that
is at least 100 ns wide. It may be much wider if one or more of
the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. Voltage supervision is then handed off
to the precise low voltage reset (PRES) circuit. When the volt-
age is high enough for PRES to release, the IMO starts.
PSoC
®
5: CY8C52 Family Data Sheet
Page 25 of 85
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