at94k10al ATMEL Corporation, at94k10al Datasheet - Page 83

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at94k10al

Manufacturer Part Number
at94k10al
Description
At94k05al 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
Manufacturer
ATMEL Corporation
Datasheet

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4.22.3.2
1138I–FPSLI–1/08
Scanning AVR RESET
When no alternate port function is present, the Input Data - ID corresponds to the PINn register
value, Output Data corresponds to the PORTn register, Output Control corresponds to the Data
Direction (DDn) register, and the PuLL-up Disable (PLD) corresponds to logic expression (DDn
OR NOT(PORTBn)).
Digital alternate port functions are connected outside the dashed box in
scan chain read the actual pin value.
Multiple sources contribute to the internal AVR reset; therefore, the AVR reset pin is not
observed. Instead, the internal AVR reset signal output from the Reset Control Unit is observed,
see
device is in general reset (Resetn or power-on) or configuration download.
Figure 4-22. Observe-only Cell
Figure
RESET CONTROL
4-22. The scanned signal is active High if AVRResetn is Low and enabled or the
UNIT
Previous
From
Cell
ShiftDR
0
1
ClockDR
AT94KAL Series FPSLIC
D
FF1
Q
Next
Cell
To
To System Logic
Figure 4-21
to make the
83

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