at94k10al ATMEL Corporation, at94k10al Datasheet - Page 131

• Manufacturer Part Number: at94k10al
• Description: At94k05al 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
• Manufacturer: ATMEL Corporation

4.29.2
1138I–FPSLI–1/08
Data Reception
Figure 4-42
Figure 4-42. UART Receiver
Note:
The receiver front-end logic samples the signal on the RXDn pin at a frequency 16 times the
baud-rate. While the line is idle, one single sample of logic 0 will be interpreted as the falling
edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first
zero-sample. Following the 1-to-0 transition, the receiver samples the RXDn pin at samples 8, 9
and 10. If two or more of these three samples are found to be logic 1s, the start bit is rejected as
a noise spike and the receiver starts looking for the next 1-to-0 transition.
XTAL
PE1/
PE3
1. n = 0, 1
shows a block diagram of the UART Receiver.
PIN CONTROL
GENERATOR
BAUD RATE
LOGIC
RXDn
(1)
BAUD x 16
DATA RECOVERY
LOGIC
UART CONTROL AND
STATUS REGISTER
DATA BUS
/16
(UCSRnB)
AT94KAL Series FPSLIC
STORE UDRn
BAUD
DATA BUS
RXCn
IRQ
UART CONTROL AND
STATUS REGISTER
SHIFT REGISTER
REGISTER (UDRn)
(UCSRnA)
10(11)-BIT RX
UART I/O DATA
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