xc6vcx75t Xilinx Corp., xc6vcx75t Datasheet - Page 44

• Manufacturer Part Number: xc6vcx75t
• Description: Virtex-6 Cxt Family Data Sheet
• Manufacturer: Xilinx Corp.

Clock Buffers and Networks
Table 53: Global Clock Switching Characteristics (Including BUFGCTRL)
Table 54: Input/Output Clock Switching Characteristics (BUFIO)
DS153 (v1.4) July 28, 2010
Advance Product Specification
Notes:
1.
2.
T
T
T
Maximum Frequency
F
T
Maximum Frequency
F
BCCCK_CE
BCCCK_S
BCCKO_O
MAX
BIOCKO_O
MAX
T
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
T
BCCCK_CE
BGCKO_O
/T
(2)
Symbol
Symbol
/T
BCCKC_S
BCCKC_CE
(BUFG delay from I0 to O) values are the same as T
and T
(1)
BCCKC_CE
(1)
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay from I0/I1 to O
Global clock tree (BUFG)
Clock to out delay from I to O
I/O clock tree (BUFIO)
Description
Description
www.xilinx.com
BCCKO_O
values.
Virtex-6 CXT Family Data Sheet
0.16/0.00
0.16/0.00
0.10
0.18
700
710
-2
-2
Speed Grade
Speed Grade
0.16/0.00
0.16/0.00
0.10
0.18
700
710
-1
-1
Units
Units
MHz
MHz
ns
ns
ns
ns
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