xc5210 Xilinx Corp., xc5210 Datasheet - Page 23

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

Figure 16. Express Mode Programming Switching Characteristics
Format
Table 6 describes the XC5200 configuration data stream.
Table 7 provides details of the internal configuration data
structure.
Configuration Sequence
Figure 17 illustrates the XC5200 start-up sequence. It is
described in detail in the sections below.
Serial Data Out
CCLK
RDY/BUSY
(DOUT)
D0-D7
CCLK
CS1
INIT
INIT (High) Setup time required
DIN Setup time required
DIN Hold time required
CCLK High time
CCLK Low time
CCLK Frequency
1
T
IC
Description
Internal INIT
2
T
BYTE
DC
0
BYTE
1
19
Clear Internal Logic
When reprogramming the XC5200 chip, a contention-free
state must be reached before memory initialization can
begin. In this state internal control lines sequence
activities in the following order: long lines are disabled,
output drivers are forced Low, and interconnect lines are
discharged. Each of these operations requires one cycle
of the 1-MHz Initialization clock. This sequencing is
important only when reprogramming, because the
contention-free state is immediately entered when
configuring from a power-on state.
BYTE
2
T
1
2
3
CD
Symbol
BYTE
3
3
T
T
T
T
T
F
IC
DC
CD
CCH
CCL
CC
Min
50
50
50
5
0
Preliminary
Max
10
LCA Filled
Units
MHz
X6154
ns
ns
ns
ns
s
R