xc5210 Xilinx Corp., xc5210 Datasheet - Page 12

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xc5210

Manufacturer Part Number
xc5210
Description
Logic Cell Array Family , Inc
Manufacturer
Xilinx Corp.
Datasheet

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XC5200 Logic Cell Array Family
Detailed Functional Description
CLB Logic
Figure 3 shows the logic in the XC5200 CLB, which
consists of four Logic Cells (LC[3:0]). Each Logic Cell
consists of an independent 4-input Lookup Table (LUT),
and a D-Type flip-flop or latch with common clock, clock
enable, and clear, but individually selectable clock polarity.
Additional logic features provided in the CLB are:
• High-speed carry propagate logic.
• High-speed pattern decoding.
• High-speed direct connection to flip-flop D-inputs.
• Each flip-flop can be programmed individually as either
• Four 3-state buffers with a shared Output Enable.
• Two 4-input LUTs can be combined to form an
5-Input Functions
Figure 5 illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
Figure 5.
a transparent, level-sensitive latch or a D flip-flop.
independent 5-input LUT.
Two LUTs in Parallel Combined to Create a 5-input Function
I1
I2
I3
I4
I5
F4
F3
F2
F1
DI
F4
F3
F2
F1
DI
F
F
F5_MUX
CO
5-Input Function
CI
8
CE
CK
D
CLR
D
FD
FD
LC0
LC1
DO
DO
X
Q
Q
X
out
Qout
X5710
Preliminary (v1.0)

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