saa7893hl-02 NXP Semiconductors, saa7893hl-02 Datasheet - Page 49

• Manufacturer Part Number: saa7893hl-02
• Description: Saa7893hl Super Audio Media Player
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 10925
Product data
Fig 50. Audio I
2
S-bus output timing.
11.2.1 DSD output
dsd_clk (= 64f s )
dsd_pcm-data
aud_clk
Table 32:
Both tables show that DSD has a fixed allocation while PCM outputs are selectable.
The I
Philips format as can be seen in the timing diagrams. The number of data bits is
always 24.
Table 33:
The wclk identification is always active for 32 clocks for each left and right sample,
except when the input clock is 384f
wclk is 48 samples active.
Remark: in this example timing of the aud_clk is 256
to logic 0. If phase is set to logic 1, the dsd_clk signal will be inverted.
Output line
DSD_PCM_8
DSD_PCM_9
DSD_PCM_10
DSD_PCM_11
Audio input
clock
256f
384f
512f
768f
s
s
s
s
2
S-bus bit stream, generated by the SAA7893HL decimation filter, is in the
Connection to a 4-channel DAC
Serial bit clock frequency
t d(o)
Rev. 02 — 26 February 2003
Pin
number
117
120
119
121
I
frequency
2f
4f
2f
4f
2f
4f
2f
4f
2
S output ‘wclk’
s
s
s
s
s
s
s
s
Mode = DSD
DSD clock
0 or 1
left channel
right channel
SAMPLE N
s
and the output sample frequency is 4f
DCLK (data bit)
frequency
128f
256f
128f
384f
128f
256f
128f
256f
s
s
s
s
s
s
s
s
Mode = PCM
PCM data/word clock
PCM data/word clock
L
L
f
f
+ R
+ R
f
f
SAMPLE N + 1
; 0 or 1
; 0 or 1
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
f
s
and DSD clock phase is set
Super audio media player
Remark
no symmetrical bit clock
48 clocks for a word
identification
SAA7893HL
MBL629
Mode = 75 Hz
0 or 1
0 or 1
75 Hz
0 or 1
s
; then the
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