saa7191b NXP Semiconductors, saa7191b Datasheet - Page 27

• Manufacturer Part Number: saa7191b
• Description: Digital Multistandard Colour Decoder, Square Pixel Dmsd-sqp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Function of the bits of Table 5
August 1996
IDEL7
“00”
HSYB7
“01”
HSYS7
“02”
HCLB7
“03”
HCLS7
“04”
HPHI7
“05”
BYPS
“06”
PREF
BPSS1
CORI1
“06”
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
to
to
to
to
to
to
to
to
IDEL0
HSYB0
HSYS0
HCLB0
HCLS0
HPHI0
BPSS0
CORI0
Increment delay time (dependent on application), step size = 4 / LLC. The delay time is
selectable from 4 / LLC ( 1 decimal multiplier) to 1024 / LLC ( 256 decimal multiplier)
equals data FF to 00 (hex). Different processing times in the chrominance channel and the
clock generation could result in phase errors in the chrominance processing by transients in
clock frequency. An adjustable delay (IDEL) is necessary if the processing time in the clock
generation is unknown.
Horizontal sync begin for 50 Hz, step size = 2 / LLC. The delay time is selectable from
C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB 1 bits.
Horizontal sync stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from
C0 (hex). Two’s complement numbers with “hidden” sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB 1 bits.
Horizontal clamp start for 50 Hz, step size = 2 / LLC. The delay time is selectable from
80 (hex).
Horizontal clamp stop for 50 Hz, step size = 2 / LLC. The delay time is selectable from
80 (hex).
Horizontal sync after PHI1 for 50 Hz, step size = 8 / LLC. The delay time is selectable from
8A (hex).
input mode select bit: 0 = CVBS mode (chrominance trap active)
use of pre-filter:
PREF may be used if chrominance trap is active.
Aperture bandpass to select different characteristics with maximums
(0.2 to 0.3
BPSS1
Coring range for high frequency components according to 8-bit luminance, Fig.15.
CORI1
382/LLC ( 191 decimal multiplier) to 128/LLC ( 64 decimal multiplier) equals data BF to
382/LLC ( 191 decimal multiplier) to 128/LLC ( 64 decimal multiplier) equals data BF to
254/LLC (+127 decimal multiplier) to +256/LLC ( 128 decimal multiplier) equals data 7F to
254/LLC (+127 decimal multiplier) to +256/LLC ( 128 decimal multiplier) equals data 7F to
936 /LLC (+117 decimal multiplier) to +944/LLC ( 118 decimal multiplier) equals data 75 to
0
0
1
1
0
0
1
1
LLC / 2):
BPSS0
0
1
0
1
CORI0
0
1
0
1
1 = S-Video mode (chrominance trap bypassed)
0 = pre-filter off; 1 = pre-filter on;
27
characteristics
)
)
)
)
coring
coring off
1 LSB
2 LSB
3 LSB
Figures 16 to 25
Product specification
SAA7191B