adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 5

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY can be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele­
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive audio
algorithms.
Entering SIMD mode also has an effect on the way data is trans­
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band­
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera­
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
(OPTI ONAL)
(OP TIONAL)
DAC
CLOCK
ADC
S DAT
S DAT
CLK
CLK
FS
FS
2
2
3
CLKI N
XTAL
CLK_ CFG 1– 0
BOOTCFG1– 0
FLAG 3– 1
DAI_ P19
DAI_ P1 8
DAI_P 20
DAI_ P1
DAI_P 2
DAI_P 3
DAI
RESE T
ADS P-21266
SRU
CLK
FS
Figure 2. ADSP-21266 System Sample Configuration
PCG A
P CGB
SCLK0
SFS0
SD0A
SD0B
S PORT0
SP ORT1
SPO RT2
S PORT3
Rev. E | Page 5 of 48 | July 2008
SPO RT4
SPORT5
J TAG
6
CLKOUT
AD15 –0
FLAG0
ALE
W R
RD
elements. These computation units support IEEE 32-bit single
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har­
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-2126x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­
gram memory (PM) bus transfers both instructions and data
(see
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a
single cycle.
ADSP-21261/ADSP-21262/ADSP-21266
Figure 1 on Page
LATCH
1). With the ADSP-2126x’s separate pro­
ADDR
W E
DATA
OE
CS
BOOT ROM
PARALLE L
I/O DEVICE
RAM, ROM
PO RT