adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 2

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21261/ADSP-21262/ADSP-21266
KEY FEATURES
Serial ports offer left-justified sample-pair and I
At 200 MHz (5 ns) core instruction rate, the ADSP-2126x oper­
Super Harvard Architecture—3 independent buses for dual
Up to 2M bits on-chip dual-ported SRAM (1M bit block 0, 1M
Up to 4M bits on-chip dual-ported mask-programmable ROM
Dual data address generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup,
Single instruction multiple data (SIMD) architecture provides
Transfers between memory and core at up to four 32-bit
Accelerated FFT butterfly computation through a multiply
DMA controller supports
IEEE 1149.1 JTAG standard test access port and on-chip
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages; avail­
Digital audio interface includes 6 serial ports, 2 precision
via 12 programmable and simultaneous receive or trans­
mit pins, which support up to 24 transmit or 24 receive I
channels of audio when all 6 serial ports (SPORTs) are
enabled or 6 full duplex TDM streams of up to 128
channels per frame
ates at 1200 MFLOPS peak/800 MFLOPS sustained
performance whether operating on fixed- or floating-point
data; 400 MMACS sustained performance at 200 MHz
data fetch, instruction fetch, and nonintrusive, zero-over­
head I/O
bit block 1) for simultaneous access by core processor and
DMA
(2M bits in block 0 and 2M bits in block 1)
reverse addressing
providing efficient program sequencing
2 computational processing elements
Concurrent execution—each processing element executes
Parallelism in buses and computational units allows single
floating- or fixed-point words per cycle, sustained
2.4 GBps bandwidth at 200 MHz core instruction rate;
900 Mbps is available via DMA
with add and subtract instruction
Up to 22 zero-overhead DMA channels for transfers
32-bit background DMA transfers at core clock speed, in
emulation
able in RoHS compliant packages
clock generators, an input data port, 3 programmable tim­
ers, and a signal routing unit
the same instruction, but operates on different data
cycle executions (with or without SIMD) of a multiply
operation; an ALU operation; a dual memory read or
write; and an instruction fetch
between the ADSP-2126x internal memory and serial
ports (12), the input data ports (IDP) (8), the SPI-compat­
ible port (1), and the parallel port (1)
parallel with full-speed processor execution
2
S support
Rev. E | Page 2 of 48 | July 2008
2
S
Asynchronous parallel/external port provides
Serial ports provide
Input data port provides an additional input path to the
Signal routing unit (SRU) provides configurable and flexible
Serial peripheral interface (SPI)
3 muxed flag/IRQ lines
1 muxed flag/timer expired line
ROM-based security features:
PLL has a wide variety of software and hardware multi­
Access to asynchronous external memory
16 multiplexed address/data lines that can support 24-bit
66M byte/sec transfer rate for 200 MHz core rate
50M byte/sec transfer rate for 150 MHz core rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLKs
50M bits/sec for a 200 MHz core and up to 37.5M bits/sec
Left-justified sample-pair and I
TDM support for telecommunications interfaces including
Up to 12 TDM stream support, each with 128 channels
Companding selection on a per channel basis in TDM mode
SHARC core configurable as either 8 channels of I
serial data or as 7 channels plus a single 20-bit wide syn­
chronous parallel data acquisition port
Supports receive audio channel data in I
connections between all DAI components, 6 serial ports,
two precision clock generators, 3 timers, an input data
port/parallel data acquisition port, 10 interrupts, 6 flag
inputs, 6 flag outputs, and 20 SRU I/O pins (DAI_Px)
Master or slave serial boot through SPI
Full-duplex operation
Master-slave mode multimaster support
Open-drain outputs
Programmable baud rates, clock polarities, and phases
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
plier/divider ratios
address external address range with 8-bit data or 16-bit
address external address range with 16-bit data
for a 150 MHz core on each data line—each has a clock,
frame sync, and 2 data lines that can be configured as
either a receiver or transmitter pair
direction for up to 24 simultaneous receive or transmit
channels (16 channels on the ADSP-21261) using 2 I
compatible stereo devices per serial port
128 TDM channel support for newer telephony inter­
faces such as H.100/H.110
per frame
sample pair, or right-justified mode
access under program control to sensitive code
2
S support, programmable
2
S, left-justified
2
S or
2
S­