adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 27

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

Memory Read—Parallel Port
The specifications in
Figure 18
memory-mapped peripherals) when the ADSP-2126x is access­
ing external memory space.
Table 25. 8-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
DAD
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
ADRH
1
1
1
CCLK
(if a hold cycle is specified, else H = 0)
are for asynchronous interfacing to memories (and
Address/Data 7–0 Setup Before RD High
Address/Data 7–0 Hold After RD High
Address 15–8 to Data Valid
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data 15–0 Hold After ALE Deasserted
ALE Deasserted to Address/Data7–0 in High-Z
RD Pulse Width
Address/Data 15–8 Hold After RD High
AD15 - 8
AD7 - 0
Table
ALE
WR
RD
25,
Table
26,
Figure
VALID ADDRESS
VALID ADDRESS
t
ADAS
t
ALEW
17, and
Figure 17. 8-Bit Memory Read Cycle
Rev. E | Page 27 of 48 | July 2008
t
ADAH
t
ALEHZ
t
ALERW
CCLK
Min
3.3
0
2 × t
1 × t
2.5 × t
0.5 × t
0.5 × t
D – 2
0.5 × t
ADSP-21261/ADSP-21262/ADSP-21266
CCLK
CCLK
t
DAD
CCLK
CCLK
CCLK
CCLK
VALID ADDRESS
– 2
– 0.5
– 2.0
– 0.8
– 0.8
– 1 + H
t
RW
VALID DATA
t
DRS
t
t
DRH
ADRH
Max
D + 0.5 × t
0.5 × t
CCLK
+ 2.0
CCLK
– 3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns