adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 2

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
KEY FEATURES
At 450 MHz core instruction rate, the ADSP-21469 performs
5 Mbits on-chip, RAM for simultaneous access by the core
DDR2 DRAM interface (16-bit) operating at maximum fre-
Dual data address generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup, provid-
VISA (variable instruction set) execution support
Single instruction multiple data (SIMD) architecture
Transfers between memory and core at a sustained
FFT accelerator implements radix-2 complex/real input, com-
IIR accelerators perform dedicated IIR filtering with high-per-
FIR accelerators perform dedicated FIR filtering with high-
In the ADSP-21469, the program sequencer can execute code
New opcodes of 16 and 32 bits are supported in addition to
INPUT/OUTPUT FEATURES
Two 8-bit wide link ports can connect to the link ports of
DMA controller supports:
External port provides glueless connection to 16-bit wide
at 2.7 GFLOPS/900 MMACs
processor and DMA
quency of half the core clock frequency
reverse addressing
ing efficient program sequencing
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
Parallelism in buses and computational units allows:
7.2 Gbytes/second bandwidth
plex output FFT with no core intervention
formance, fixed- and floating-point processing capabilities
with no core intervention
performance, fixed- and floating-point processing capabil-
ities with no core intervention
directly from external memory bank 0 (SRAM, as well as
DDR2 DRAM). This allows more options to a user in terms
of code and data storage.
the existing 48 bit opcodes. Variable Instruction Set Archi-
tecture (VISA) execution from external DDR2 DRAM
memory is also supported.
other SHARCs or peripherals. Link ports are bidirectional
programmable ports having eight data lines, an acknowl-
edge line and a clock line. Link ports can operate at a
maximum frequency of 166 MHz.
36 DMA channels for transfers between ADSP-21469 inter-
DMA transfers at peripheral clock speed, in parallel with
synchronous DDR2 DRAM using a dedicated DDR2 DRAM
controller, and 8-bit wide asynchronous memory devices
using asynchronous memory interface (AMI)
the assembly level
Single cycle executions (with or without SIMD) of a mul-
tiply operation, an ALU operation, a dual memory read
or write, and an instruction fetch
nal memory and a variety of peripherals
full-speed processor execution
—
PROCESSOR CORE
Rev. PrB | Page 2 of 56 | November 2008
Digital audio interface (DAI) includes eight serial ports, four
Digital peripheral interface (DPI) includes, two timers, one
Eight dual data line serial ports— each has a clock, frame
TDM support for telecommunications interfaces including
Up to 16 TDM stream support, each with 128 channels per
Companding selection on a per channel basis in TDM mode
Input data port (IDP), configurable as eight channels of serial
Signal routing unit provides configurable and flexible con-
4 independent asynchronous sample rate converters (ASRC).
2 muxed flag/IRQ lines
1 muxed flag/IRQ /AMI_MS pin
1 muxed flag/Timer expired line /AMI_MS pin
S/PDIF-compatible digital audio receiver/transmitter sup-
Pulse-width modulation provides:
PLL has a wide variety of software and hardware multi-
Thermal diode to monitor die temperature
Available in 19 mm by 19 mm PBGA package (see
Programmable wait state options (for AMI): 2 to 31
Delay-line DMA engine maintains circular buffers in
16-bit data access for synchronous DDR2 DRAM
8-bit data access for asynchronous memory
4 memory select lines allows multiple external memory
precision clock generators, an input data port, an S/PDIF
transceiver, and a signal routing unit
UART, and two SPI ports, and a two-wire interface port
Outputs of PCG’s A and B can be routed through DAI pins
Outputs of PCG's C and D can be driven on to DAI as well as
DPI pins
sync, and two data lines that can be configured as either a
receiver or transmitter pair
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
frame
data or seven channels of serial data and up to a 20-bit
wide parallel data channel
nections between the various peripherals and the DAI/DPI
components
Each converter has separate serial input and output ports,
a de-emphasis filter providing up to –128 dB SNR perfor-
mance, stereo sample rate converter and supports left-
justified, I2S, TDM, and right-justified modes and 24-, 20-,
18-, and 16-audio data word lengths.
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I
16-, 18-, 20- or 24-bit word widths (transmitter)
16 PWM outputs configured as four groups of four outputs
supports center-aligned or edge-aligned PWM waveforms
plier/divider ratios
Guide on Page
DDR2_CLK cycles
external memory with tap/offset based reads
devices
Preliminary Technical Data
2
56)
S or right-justified serial data input with
Ordering