adv7189b Analog Devices, Inc., adv7189b Datasheet - Page 60

• Manufacturer Part Number: adv7189b
• Description: Multiformat Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

ADV7189B
PIXEL PORT CONFIGURATION
The ADV7189B has a very flexible pixel port that can be config-
ured in a variety of formats to accommodate downstream ICs.
T able 79 and
2 5 1 H
ADV7189B pins can have in different modes of operation.
The ordering of components, for example, Cr vs. Cb,
CHA/B/C, can be changed. Refer to the
Cr/Cb, Address 0x27[7] section.
positions for the Cr/Cb components.
OF_SEL[3:0] Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7189B pixel port can be configured
are under the control of OF_SEL[3:0]. See
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data
rate of 13.5 MHz (0001, 0010), the clock frequency on the
LLC1 pin stays at the higher rate of 27 MHz. For information
on outputting the nominal 13.5 MHz clock on the LLC1 pin,
see the
Address 0x8F[6:4] section.
Table 79. P19 to P0 Output/Input Pin Mapping
Video Out, 8-Bit, 4:2:2
Video Out, 10-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Video Out, 20-Bit, 4:2:2
Table 80. Standard Definition Pixel Port Modes
OF_SEL[3:0]
0000
0001
0010
0011 (default)
0110-1111
Processor, Format, and Mode
Function
L LC1 Output Selection, LLC_PAD_SEL[2:0],
2 5 6 H
T able 80 summarize the various functions that the
2 5 2 H
Format
10-Bit at LLC1 4:2:2
20-Bit at LLC2 4:2:2
16-Bit at LLC2 4:2:2
8-Bit at LLC1 4:2:2
Reserved
T able 79 indicates the default
2 5 4 H
19
S WPC Swap Pixel
2 5 3 H
18
T able 80 for details.
2 5 5 H
17
YCrCb[7:0] OUT
Y[7:0] OUT
16
YCrCb[9:0] OUT
P[19:12]
YCrCb[9:2]
Y[9:2]
Y[7:0]
YCrCb[7:0]
Y[9:0] OUT
Rev. B | Page 60 of 104
15
14
13
SWPC Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F[6:4]
The following I
LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-/20-bit) output modes. See OF_SEL[3:0] for additional
information. The LLC2 signal and data on the data bus are
synchronized. By default, the rising edge of LLC1/LLC2 is
aligned with the Y data; the falling edge occurs when the data
bus holds C data. The polarity of the clock, and therefore the
Y/C assignments to the clock edges, can be altered by using
the Polarity LLC pin.
When LLC_PAD_SEL[2:0] is 000 (default), the output is
nominally 27 MHz LLC on the LLC1 pin.
When LLC_PAD_SEL[2:0] is 101, the output is nominally
13.5 MHz LLC on the LLC1 pin.
P[19:10]
Data Port Pins P[19:0]
12
Three-state
Three-state
P[11:10]
YCrCb[1:0]
Y[1:0]
11
Pixel Port Pins P[19:0]
Reserved. Do not use.
2
C write allows the user to select between the
10
9
8
P[9:2]
Three-State
CrCb[9:2]
CrCb[7:0]
Three-state
7
CrCb[7:0] OUT
6
CrCb[9:0] OUT
5
P9[9:0]
4
P[1:0]
Three-State
CrCb[1:0]
Three-state
Three-state
3
2
1
0